參數(shù)資料
型號(hào)： AMD-K5
廠商： Advanced Micro Devices, Inc.
英文描述： 32-Bit Superior Price/Performance Value Microprocessor(32位高性/價(jià)比微處理器)
中文描述： 32位卓越的價(jià)格/性能值微處理器（32位高性/價(jià)比微處理器）
文件頁(yè)數(shù)： 30/100頁(yè)
文件大?。?/td> 2533K
代理商： AMD-K5
20
AMD-K5 Processor Data Sheet
18522F/0—Jan1997
PRELIMINARY INFORMATION
HOLD
Bus Hold Request
The HOLD signal is used to request the processor bus. When
this signal is asserted, the processor will complete all pending
bus cycles, float the bus, and assert the HLDA signal. This sig-
nal is not recognized during locked cycles. (See Switching
Characteristics
t
24
and
t
25b
.)
Input
IERR
Internal Error
IERR indicates internal parity errors and functional redun-
dancy errors. Internal parity errors will cause IERR to be
asserted for one clock, and the processor will halt. Functional
redundancy errors, when configured as a Checker, will cause
IERR to be asserted in the second clock after the mismatched
output value was detected.
Output
IGNNE
Ignore Numeric Error
The IGNNE signal is used in conjunction with the NE bit in
CR0 to control response to numeric errors in the floating-point
unit. Numeric errors are handled internally when the NE bit is
set. When the NE bit is not set, errors are reported if IGNNE is
asserted and ignored when negated. (See Switching Character-
istics t
28
and
t
29
.)
Input
INIT
Initialize
The processor will perform a warm initialization when the INIT
signal is asserted. The INIT signal is similar to the RESET sig-
nal except that the data buffers, data cache, floating-point reg-
isters, instruction cache, and SMBASE registers are not
modified. The processor will perform a self-test if the INIT sig-
nal is sampled High at the falling edge of RESET.
Input
INTR
Maskable Interrupt
The INTR signal is used to generate interrupts. The interrupt
number is transferred to the processor during the interrupt
acknowledge cycle. To ensure that interrupts are acknowl-
edged, the INTR signal must be asserted until a locked inter-
rupt acknowledge cycle is complete. The INTR can be masked
by clearing the IF bit in the EFLAGS register. (See Switching
Characteristics t
26
and
t
27
.)
Input
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