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參數(shù)資料
| 型號： | AMD-K5 |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | 32-Bit Superior Price/Performance Value Microprocessor(32位高性/價比微處理器) |
| 中文描述： | 32位卓越的價格/性能值微處理器（32位高性/價比微處理器） |
| 文件頁數(shù)： | 40/100頁 |
| 文件大?。?/td> | 2533K |
| 代理商： | AMD-K5 |
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30
AMD-K5 Processor Data Sheet
18522F/0—Jan1997
PRELIMINARY INFORMATION
Normal Execution
State
In this state, the AMD-K5 processor operates at full speed. All
clocks are running.
Halt/Auto-Power-
Down State
In this state, most internal clocks are stopped. The Phase Lock
Loop (PLL) is operating and certain bus interface components
are clocked. Instruction execution is disabled. This aids in
timely detection of inquire cycles and HOLD/HLDA sequences,
while greatly reducing power consumption.
The Halt/Auto-Power-Down State is entered from normal exe-
cution state by executing the HALT instruction in Real mode
or Protected mode. The clock state will return to normal execu-
tion state when an interrupt, non-maskable interrupt, system
management interrupt, power-on reset, or soft reset is detected
(INTR, NMI, SMI, RESET, or INIT, respectively). The clock
state may temporarily transition from Halt/Auto-Power-Down
State to Stop Clock Snoop State to process an inquire cycle or
to Stop Grant State in response to a STPCLK. In these cases,
the clock state will return to Halt/Auto-Power-Down State and
wait for one of the interrupt conditions when the secondary
condition is removed.
Stop Grant State
In this state, most internal clocks are stopped. The PLL is oper-
ating and certain bus interface components are clocked.
Instruction execution is disabled. This allows timely detection
of inquire cycles and HOLD/HLDA sequences, while greatly
reducing power consumption.
The Stop Grant State is entered from Normal Execution State
or Halt/Auto-Power-Down State by asserting the STPCLK pin.
When STPCLK is sampled as asserted, the current instruction
is completed, all processing is stopped, a Stop Grant bus cycle
is generated, and the clock is shut down. The clock state will
return to its previous state when STPCLK is negated. Once
asserted, STPCLK must not be negated until the Stop Grant
Acknowledge special cycle is seen. The clock state may tempo-
rarily transition from Stop Grant State to Stop Clock Snoop
State to process an inquire cycle, or to Stop Clock State to pro-
cess a Stop Clock request. In these cases, the clock state will
return to Stop Grant State when the secondary condition is
removed.
STPCLK is treated as the lowest priority external interrupt. If
a higher priority external interrupt exists (power-on reset, soft
reset, flush, system management interrupt, non-maskable
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AMD-K5-PR100ABQ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32-Bit Microprocessor |
| AMD-K5-PR120ABR | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32-Bit Microprocessor |
| AMD-K5-PR133ABQ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32-Bit Microprocessor |
| AMD-K5-PR133ABR | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32-Bit Microprocessor |
| AMD-K5-PR166ABX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32-Bit Microprocessor |
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