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參數(shù)資料
| 型號： | AD9558/PCBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 93/104頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD9558 |
| 產(chǎn)品變化通告： | AD9558 Minor Metal Mask Change 17/Apr/2012 |
| 設(shè)計資源： | AD9558 Eval Brd BOM AD9558 Schematic |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | * |
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Data Sheet
AD9558
Rev. B | Page 89 of 104
REFB Profile (Register 0x0740 to Register 0x0766)
REFB Profile Register 0x0740 to Register 0x0766 are identical to REFA Profile Register 0x0700 to Register 0x0726.
REFC Profile (Register 0x0780 to Register 0x07A6)
REFC Profile Register 0x0780 to Register 0x07A6 are identical to REFA Profile Register 0x0700 Register 0x0726.
REFD Profile (Register 0x07C0 to Register 0x07E6)
REFD Profile Register 0x07C0 to Register 0x07E6 are identical to REFA Profile Register 0x0700 to Register 0x0726.
OPERATIONAL CONTROLS (REGISTER 0x0A00 TO REGISTER 0x0A10)
Table 89. General Power-Down
Address
Bits
Bit Name
Description
0x0A00
7
Soft reset exclude regmap
Resets device but retains programmed register values (default: not reset)
6
DCO power-down
Places DCO in deep sleep mode (default: not powered down)
5
SYSCLK power-down
Places SYSCLK input and PLL in deep sleep mode (default: not powered down)
5
Reference input power-down
Places reference clock inputs in deep sleep mode (default: not powered down)
3
TDC power-down
Places the time-to-digital converter in deep sleep mode (default: not powered down)
2
APLL power-down
Places the output PLL in deep sleep mode (default: not powered down)
1
Clock dist power-down
Places the clock distribution outputs in deep sleep mode (default: not powered down)
0
Full power-down
Places the entire device in deep sleep mode (default: not powered down)
Table 90. Loop Mode
Address
Bits
Bit Name
Description
0x0A01
7
Reserved
Reserved.
6
User holdover
Forces the device into holdover mode (default: not forced holdover mode).
If a tuning word history is available, then the history tuning word specifies the DCO
output frequency. Otherwise, the free run frequency tuning word register specifies the
DCO output frequency.
The phase and frequency lock detectors are forced into the unlocked state.
5
User freerun
Forces the device into user free run mode (default is not forced user free run mode).
The free run frequency tuning word register specifies the DCO output frequency. When
the user freerun bit is set, it overrides the user holdover bit (Address 0x0A01, Bit 6).
[4:2]
REF switchover mode
Selects the operating mode of the reference switching state machine.
Reference Switchover Mode, Bits[2:0]
Register 0x0A01[4:2]
Reference Selection Mode
000 (default)
001
010
011
100
101
110
111
Automatic revertive mode
Automatic nonrevertive mode
Manual reference select
(with automatic fallback mode)
Manual reference select mode
(with auto-holdover)
Full manual mode (no auto-holdover)
Not used
[1:0]
User reference in manual
switchover mode
Input reference when REF switchover mode bits (Register 0x0A01, Bits[4:2]) = 010, 011, or 100.
00 (default) = Input Reference A.
01 = Input Reference B.
10 = Input Reference C.
11 = Input Reference D.
Table 91. Cal/Sync Distribution
Address
Bits
Bit Name
Description
0x0A02
[7:2]
Reserved
Default: 0x00
1
Soft sync clock distribution
Setting this bit initiates synchronization of the clock distribution output (default: 0b).
Nonmasked outputs stall when value is 1b; restart is initialized on 1b to 0b transition.
0
Reserved
Default: 0b.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9559 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual PLL, Quad Input, Multiservice Line Card Adaptive Clock Translator |
| AD9559/PCBZ | 功能描述:時鐘和定時器開發(fā)工具 Multi-protocol line card dual clock RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Modules 類型:Clock Conditioners 工具用于評估:LMK04100B 頻率:122.8 MHz 工作電源電壓:3.3 V |
| AD9559BCPZ | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 Multi-protocol line card dual clock RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| AD9559BCPZ-REEL7 | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 Multi-protocol line card dual clock RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| AD9559PCBZ | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual PLL, Quad Input, Multiservice Line Card Adaptive Clock Translator |
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