參數(shù)資料
型號(hào)： AD9558/PCBZ
廠商： Analog Devices Inc
文件頁數(shù)： 40/104頁
文件大?。?/td> 0K
描述： BOARD EVAL FOR AD9558
產(chǎn)品變化通告： AD9558 Minor Metal Mask Change 17/Apr/2012
設(shè)計(jì)資源： AD9558 Eval Brd BOM
AD9558 Schematic
標(biāo)準(zhǔn)包裝： 1
系列： *
AD9558
Data Sheet
Rev. B | Page 40 of 104
FRAME SYNCHRONIZATION
The AD9558 provides frame synchronization function/mode.
With this function, the AD9558 can take a pair consisting of a
reference clock and a 2 kHz or 8 kHz frame pulse as input signals
and generate a pair consisting of a synchronized output clock
and an output frame pulse while the output frame pulse is
synchronized with the input frame pulse also. The reference
clock is used to synthesize the output clock and output frame
pulse through DPLL/output PLL/distribution and the input frame
pulse is used to control the phase of the output frame pulse.
Frame synchronization is not supported in the soft or hard pin
control mode.
REFERENCE CONFIGURATION IN FRAME
SYNCHRONIZATION MODE
In frame synchronization mode, four AD9558 reference inputs
(REFA/REFB/REFC/REFD) are arranged into two pairs of signals:
REFA and REFC form a pair of input clock/input frame pulse
with REFA as the input clock, and REFC as the frame pulse.
REFB and REFD form the second pair of input clock/ input
frame pulse with REFB as the input clock and REFD is the frame
pulse. During reference switchover, only two input clocks, REFA
and REFB, are assigned with a priority index. The two frame
pulses, REFC and REFD, are not assigned with the priority index
(the priority register bits in the profiles associated with input
frame pulse are ignored). Each pair of input clock/ frame pulse
participates in the reference selection as a group, and the valid
state and priority of the pair are used in determining the reference
selection. The priority of the pair is indicated by the priority
index of the input clock in the pair.
Users have the option to either include or exclude the valid state
of input frame pulse in the reference selection by programming
the validate Fsync reference bit (Register 0x0641[3]). When
Register 0x0641[3] is programmed to 1b, the valid state of the
input frame pulse and the valid state of the paired input clock
are logically ANDed and the result is used to indicate the valid
state of the pair. When validate Fsync ref is programmed to 0b,
the valid state of the input frame pulse is excluded in reference
selection and only the valid state of the input clock in the pair is
used to indicate the valid state of the pair. The valid pair with the
higher priority index is selected as the DPLL reference and input
frame pulse to control the phase of the output frame pulse. If no
pair is valid, the selection does not change and DPLL is switched
to either holdover or free run mode, and the phase of the output
frame pulse is not controlled by any of the input frame pulses.
The five reference switchover modes for frame synchronization
mode is the same as for normal mode.
CLOCK OUTPUTS IN FRAME SYNCHRONIZATION
MODE
The AD9558 has six outputs (OUT0 to OUT5). In frame sync
mode, the OUT0 and OUT5 form the pair of output clock
(OUT0) and output frame pulse (OUT5). The frequency of
OUT0 is required to have the integer relation with the frequency of
the OUT5 (fOUT0 = M × fOUT5). The rest of the outputs (OUT1 to
OUT4) do not participate in frame synchronization mode and
are programmed and synchronized with each other the same as
in normal mode (except for
A
SYNCE
A
function). However, OUT1
to OUT4 should not be synchronized with the OUT0/OUT5.
CONTROL REGISTERS FOR FRAME
SYNCHRONIZATION MODE
The frame synchronization function is enabled by setting
Register 0x0640[0] to 1b. When Register 0x0640[0] = 1b, the
following occurs:
The frame synchronization control bits (Register
0x0641[3:0]) are enabled.
The
A
SYNCE
A
pin switches from
A
SYNCE
A
function to frame
A
SYNCE
A
function. In frame synchronization mode,
A
SYNCE
A
cannot be used as clock distribution synchronization
function as it is in normal mode. Instead it is used as the
frame synchronization arm function.
When the AD9558 is in frame synchronization mode, the frame
synchronization function can be armed by either the
A
SYNCE
A
pin
or the arm soft Fsync bit (Register 0x0641[0]), which is selected
by the Fsync arm method bit (Register 0x0641[1]. A value of 0b
(which is the default) selects the
A
SYNCE
A
pin as the arm method.
If
A
SYNCE
A
is selected as arm method,
A
SYNCE
A
= low means armed;
if the register is selected as arm method, Register 0x0641[0] = 1b
means armed. ARM means that once armed, the output frame
pulse is edge aligned with the paired output clock edge after the
rising edge of the input frame pulse.
LEVEL SENSITIVE MODE AND ONE-SHOT MODE
The frame synchronization can operate in level sensitive or one-
shot mode as determined by the Fsync one shot bit (Register
0x0641[2]). When in level sensitive mode (Register 0x0641[2] =
0b) and the frame sync ARM signal is high, each rising edge of
the selected input frame pulse signal is used to control the
phase of the output frame pulse. When in one-shot mode, after
the frame sync ARM signal is high, only the immediate next
rising edge of the selected input frame pulse signal is used to
control the phase of the output frame pulse (one time phase
alignment). After that, the phase of the output frame pulse is
not controlled by the selected input frame pulse. Instead, it
follows the phase of the input clock of M3 divider. In either
alignment control mode, the resolution of the phase realignment
between the input frame pulse and the output frame pulse is
one clock cycle of the paired clock output.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD9559 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual PLL, Quad Input, Multiservice Line Card Adaptive Clock Translator
AD9559/PCBZ 功能描述:時(shí)鐘和定時(shí)器開發(fā)工具 Multi-protocol line card dual clock RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Modules 類型:Clock Conditioners 工具用于評估:LMK04100B 頻率:122.8 MHz 工作電源電壓:3.3 V
AD9559BCPZ 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 Multi-protocol line card dual clock RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56
AD9559BCPZ-REEL7 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 Multi-protocol line card dual clock RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56
AD9559PCBZ 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual PLL, Quad Input, Multiservice Line Card Adaptive Clock Translator
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