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參數(shù)資料
| 型號： | AD9558/PCBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 59/104頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD9558 |
| 產(chǎn)品變化通告： | AD9558 Minor Metal Mask Change 17/Apr/2012 |
| 設(shè)計資源： | AD9558 Eval Brd BOM AD9558 Schematic |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | * |
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AD9558
Data Sheet
Rev. B | Page 58 of 104
POWER SUPPLY PARTITIONS
The AD9558 power supplies are divided into four groups:
DVDD3, DVDD, AVDD3, and AVDD. All power and ground
pins should be connected, even if certain blocks of the chip are
powered down.
RECOMMENDED CONFIGURATION FOR 3.3 V
SWITCHING SUPPLY
A popular power supply arrangement is to power the AD9558
with the output of a 3.3 V switching power supply.
When the AD9558 is powered using 3.3 V switching power
supplies, all of the 3.3 V supplies can be connected to the 3.3 V
switcher output, and a 0.1 F bypass capacitor should be placed
adjacent to each 3.3 V power supply pin.
CONFIGURATION FOR 1.8 V SUPPLY
When 1.8 V supplies are preferred, it is recommended that an
LDO regulator, such as the ADP222, be used to generate the
1.8 V supply from the 3.3 V supply.
The ADP222 offers excellent power supply rejection in a small
(2 mm × 2 mm) package. It has two 1.8 V outputs. One output
can be used for the DVDD pins (Pin 6, Pin 34, and Pin 35), and
the other output can drive the AVDD pins.
The ADP7104 is another good choice for converting 3.3 V to
1.8 V. The close-in noise of the ADP7104 is lower than that of
the ADP222; therefore, it may be better suited for applications
where close-in phase noise is critical and the AD9557 DPLL loop
bandwidth is <50 Hz. In such cases, all 1.8 V supplies can be
connected to one ADP7104.
Use of Ferrite Beads on 1.8 V Supplies
To ensure the very best output-to-output isolation, one ferrite
bead should be used instead of a bypass capacitor for each of
the following AVDD pins: Pin 12, Pin 22, Pin 29, and Pin 30. The
ferrite beads should be placed in between the 1.8 V LDO output
and each pin listed above. Ferrite beads that have low (<0.7 )
dc resistance and approximately 600 impedance at 100 MHz
are suitable for this application.
See Table 2 for the current consumed by each group. Refer to
Figure 20, Figure 21, and Figure 22 for information on the
power consumption vs. output frequency.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9559 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual PLL, Quad Input, Multiservice Line Card Adaptive Clock Translator |
| AD9559/PCBZ | 功能描述:時鐘和定時器開發(fā)工具 Multi-protocol line card dual clock RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Modules 類型:Clock Conditioners 工具用于評估:LMK04100B 頻率:122.8 MHz 工作電源電壓:3.3 V |
| AD9559BCPZ | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 Multi-protocol line card dual clock RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| AD9559BCPZ-REEL7 | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 Multi-protocol line card dual clock RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| AD9559PCBZ | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual PLL, Quad Input, Multiservice Line Card Adaptive Clock Translator |
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