參數(shù)資料
型號： AD9558/PCBZ
廠商： Analog Devices Inc
文件頁數(shù)： 87/104頁
文件大?。?/td> 0K
描述： BOARD EVAL FOR AD9558
產(chǎn)品變化通告： AD9558 Minor Metal Mask Change 17/Apr/2012
設(shè)計(jì)資源： AD9558 Eval Brd BOM
AD9558 Schematic
標(biāo)準(zhǔn)包裝： 1
系列： *
Data Sheet
AD9558
Rev. B | Page 83 of 104
Table 70. Distribution OUT1 Setting
Address
Bits
Bit Name
Description
0x0505
7
Reserved
Reserved; default: 0b
[6:4]
OUT1 format
Select the operating mode of OUT1
000 = PD, tristate
001 (default) = HSTL
010 = LVDS
011 = reserved
100 = CMOS, both outputs active
101 = CMOS, P output active, N output power-down
110 = CMOS, N output active, P output power-down
111 = reserved
[3:2]
OUT1 polarity
Configure the OUT1 polarity in CMOS mode and are active in CMOS mode only
00 (default) = positive, negative
01 = positive, positive
10 = negative, positive
11 = negative, negative
1
OUT1 drive strength
Controls the output drive capability of OUT1
0 (default) = LVDS: 3.5 mA nominal
1 = LVDS: 4.5 mA nominal (LVDS boost mode)
No CMOS control because OUT1 is 1.8 V CMOS only
0
Enable OUT1
Setting this bit enables the OUT1 driver (default is disabled)
0x0506
7
Reserved
Reserved; default: 0b
[6:4]
OUT2 format
Select the operating mode of OUT2
000 = PD, tristate
001 (default) = HSTL
010 = LVDS
011 = reserved
100 = CMOS, both outputs active
101 = CMOS, P output active, N output power-down
110 = CMOS, N output active, P output power-down
111 = reserved
[3:2]
OUT2 polarity
Configure the OUT2 polarity in CMOS mode and are active in CMOS mode only
00 (default) = positive, negative
01 = positive, positive
10 = negative, positive
11 = negative, negative
1
OUT2 drive strength
Controls the output drive capability of OUT2
0 (default) = LVDS: 3.5 mA nominal
1 = LVDS: 4.5 mA nominal (LVDS boost mode)
No CMOS control because OUT2 is 1.8 V CMOS only
0
Enable OUT2
Setting this bit enables the OUT2 driver (default is disabled)
Table 71. Distribution Channel 1 Divider Setting
Address
Bits
Bit Name
Description
0x0507
[7:0]
Channel 1 divider
The same control for Channel 1 divider as in Register 0x0502 for Channel 0 divider
0x0508
[7:0]
Channel 1 divider
The same control for Channel 1 divider as in Register 0x0503 for Channel 0 divider
0x0509
[7:0]
Channel 1 divider
The same control for Channel 1 divider as in Register 0x0504 for Channel 0 divider
Table 72. Clock Distribution Channel 2 and OUT3, OUT4 Driver Settings
Address
Bits
Bit Name
Description
0x050A
[7:0]
OUT3
The same control for OUT3 as in Register 0x0505 for OUT1
0x050B
[7:0]
OUT4
The same control for OUT4 as in Register 0x0505 for OUT1
0x050C
[7:0]
Channel 2 divider
The same control for Channel 2 divider as in Register 0x0502 for Channel 0 divider
0x050D
[7:0]
Channel 2 divider
The same control for Channel 2 divider as in Register 0x0503 for Channel 0 divider
0x050E
[7:0]
Channel 2 divider
The same control for Channel 2 divider as in Register 0x0504 for Channel 0 divider
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD9559 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual PLL, Quad Input, Multiservice Line Card Adaptive Clock Translator
AD9559/PCBZ 功能描述:時(shí)鐘和定時(shí)器開發(fā)工具 Multi-protocol line card dual clock RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Modules 類型:Clock Conditioners 工具用于評估:LMK04100B 頻率:122.8 MHz 工作電源電壓:3.3 V
AD9559BCPZ 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 Multi-protocol line card dual clock RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56
AD9559BCPZ-REEL7 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 Multi-protocol line card dual clock RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56
AD9559PCBZ 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual PLL, Quad Input, Multiservice Line Card Adaptive Clock Translator
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