參數(shù)資料
型號： AD9558/PCBZ
廠商： Analog Devices Inc
文件頁數(shù)： 92/104頁
文件大?。?/td> 0K
描述： BOARD EVAL FOR AD9558
產(chǎn)品變化通告： AD9558 Minor Metal Mask Change 17/Apr/2012
設計資源： AD9558 Eval Brd BOM
AD9558 Schematic
標準包裝： 1
系列： *
AD9558
Data Sheet
Rev. B | Page 88 of 104
Table 83. DPLL Loop BW Scaling Factor—REFA Profile1
Address
Bits
Bit Name
Description
0x070F
[7:0]
DPLL loop BW scaling factor
(unit of 0.1 Hz)
Digital PLL loop bandwidth scaling factor, Bits[7:0] (default: 0xF4).
0x0710
[7:0]
Digital PLL loop bandwidth scaling factor, Bits[15:8] (default: 0x01).
The default for Register 0x070F to Register 0x0710 = 0x01F4 = 500 (50 Hz loop bandwidth).
The loop bandwidth should always be less than the DPLL phase detector frequency
divided by 20.
0x0711
[7:1]
Reserved
Default: 0x00.
0
BW scaling factor
Digital PLL loop bandwidth scaling factor, Bit 16 (default: 0b).
1
Note that the default DPLL loop BW is 50.4 Hz.
Table 84. R-Divider—REFA Profile1
Address
Bits
Bit Name
Description
0x0712
[7:0]
R divider
DPLL integer reference divider (minus 1), Bits[7:0] (default: 0xC5)
0x0713
[7:0]
DPLL integer reference divider, Bits[15:8] (default: 0x00)
0x0714
[7:5]
Reserved
Reserved. Default: 0x0
4
Enable REFA div2
Enables the reference input divide-by-2 for REFA
0 = bypass the divide-by-2 (default)
1 = enable the divide-by-2
[3:0]
R divider
DPLL integer reference divider, Bits[19:16] (default: 0x0).
The default for Register 0x0712 to Register 0x0714 = 0x000C5 = 197 (which equals R = 198).
1
Note that the value stored in the R-divider register yields an actual divide ratio of one more than the programmed value.
Table 85. Integer Part of Fractional Feedback Divider N1—REFA Profile1
Address
Bits
Bit Name
Description
0x0715
[7:0]
Integer Part N1
DPLL integer feedback divider (minus 1), Bits[7:0] (default: 0x6B).
0x0716
[7:0]
DPLL integer feedback divider, Bits[15:8] (default: 0x07).
0x0717
[7:1]
Reserved
Reserved. Default: 0x00.
0
Integer Part N1
DPLL integer feedback divider, Bit 16 (default: 0b).
The default for Register 0x0715 to Register 0x717 = 0x0076B (which equals N1 = 1900).
1
Note that the value stored in the N1-divider register yields an actual divide ratio of one more than the programmed value.
Table 86. Fractional Part of Fractional Feedback Divider FRAC1—REFA Profile
Address
Bits
Bit Name
Description
0x0718
[7:0]
Digital PLL fractional feedback
divider—FRAC1
The numerator of the fractional-N feedback divider, Bits[7:0] (default: 0x04)
0x0719
[7:0]
The numerator of the fractional-N feedback divider, Bits[15:8] (default: 0x00)
0x071A
[7:0]
The numerator of the fractional-N feedback divider, Bits[23:16] (default: 0x00)
Table 87. Modulus of Fractional Feedback Divider MOD1—REFA Profile
Address
Bits
Bit Name
Description
0x071B
[7:0]
Digital PLL feedback divider
modulus—MOD1
The denominator of the fractional-N feedback divider, Bits[7:0] (default: 0x05)
0x071C
[7:0]
The denominator of the fractional-N feedback divider, Bits[15:8] (default: 0x00)
0x071D
[7:0]
The denominator of the fractional-N feedback divider, Bits[23:16] (default: 0x00)
Table 88. Phase and Frequency Lock Detector Controls—REFA Profile
Address
Bits
Bit Name
Description
0x071E
[7:0]
Phase lock threshold
Phase lock threshold, Bits[7:0] (default: 0xBC); default of 0x02BC = 700 ps
0x071F
[7:0]
Phase lock threshold, Bits[15:8] (default: 0x02)
0x0720
[7:0]
Phase lock fill rate
Phase lock fill rate, Bits[7:0] (default:0x0A = 10 code/PFD cycle)
0x0721
[7:0]
Phase lock drain rate
Phase lock drain rate, Bits[7:0] (default: 0x0A = 10 code/PFD cycle)
0x0722
[7:0]
Frequency lock threshold
Frequency lock threshold, Bits[7:0] (default: 0xBC); default of 0x02BC = 700 ps
0x0723
[7:0]
Frequency lock threshold, Bits[15:8] (default: 0x02)
0x0724
[7:0]
Frequency lock threshold, Bits[23:16] (default: 0x00)
0x0725
[7:0]
Frequency lock fill rate
Frequency lock fill rate, Bits[7:0] (default: 0x0A = 10 code/PFD cycle)
0x0726
[7:0]
Frequency lock drain rate
Frequency lock drain rate bits[7:0] (default: 0x0A = 10 code/PFD cycle)
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD9559 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual PLL, Quad Input, Multiservice Line Card Adaptive Clock Translator
AD9559/PCBZ 功能描述:時鐘和定時器開發(fā)工具 Multi-protocol line card dual clock RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Modules 類型:Clock Conditioners 工具用于評估:LMK04100B 頻率:122.8 MHz 工作電源電壓:3.3 V
AD9559BCPZ 功能描述:時鐘發(fā)生器及支持產(chǎn)品 Multi-protocol line card dual clock RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56
AD9559BCPZ-REEL7 功能描述:時鐘發(fā)生器及支持產(chǎn)品 Multi-protocol line card dual clock RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56
AD9559PCBZ 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual PLL, Quad Input, Multiservice Line Card Adaptive Clock Translator
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