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參數(shù)資料
| 型號： | AD9558/PCBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 36/104頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR AD9558 |
| 產(chǎn)品變化通告： | AD9558 Minor Metal Mask Change 17/Apr/2012 |
| 設(shè)計資源： | AD9558 Eval Brd BOM AD9558 Schematic |
| 標準包裝： | 1 |
| 系列： | * |
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Data Sheet
AD9558
Rev. B | Page 37 of 104
OUTPUT PLL (APLL)
A diagram of the output PLL (APLL) is shown in Figure 39.
LF CAP
VCO2
3.35GHz TO 4.05GHz
PFD
FROM DPLL
TO CLOCK
DISTRIBUTION
LF
CP
INTEGER DIVIDER
OUTPUT PLL DIVIDER (APLL)
÷N2
09758-
138
LF_VCO2
Figure 39. Output PLL Block Diagram
The APLL provides the frequency upconversion from the DPLL
output to the 3.35 GHz to 4.05 GHz range, while also providing
noise filtering on the DPLL output. The APLL reference input is
the output of the DPLL. The feedback divider is an integer divider.
The loop filter is partially integrated with the one external 6.8 nF
capacitor. The nominal loop bandwidth for this PLL is 250 kHz,
with 68 degrees of phase margin.
The frequency wizard that is included in the evaluation software
configures the APLL, and the user should not need to make
changes to the APLL settings. However, there may be special cases
where the user may wish to adjust the APLL loop bandwidth to
meet a specific phase noise requirement. The easiest way to change
the APLL loop BW is to adjust the APLL charge pump current
in Register 0x0400. There is sufficient stability (68 of phase
margin) in the APLL default settings to permit a broad range of
adjustment without causing the APLL to be unstable. The user
should contact Analog Devices directly if more detail is needed.
Calibration of the APLL must be performed at startup and
when the nominal input frequency to the APLL changes by
more than ±100 ppm, although the APLL maintains lock
over voltage and temperature extremes without recalibration.
Calibration centers the dc operating voltage at the input to the
APLL VCO.
APLL calibration at startup can be accomplished during initial
register loading by following the instructions in the Device
section of this datasheet.
To recalibrate the APLL VCO after the chip has been running,
the user should first input the new settings (if any). Ensure that
the system clock is still locked and stable, and that the DPLL is
in free run mode with the free run tuning word set to the same
output frequency that is used when the DPLL is locked.
Use the following steps to calibrate the APLL VCO:
1. Ensure that the system clock is locked and stable.
2. Ensure that the DPLL is in user free run mode
(Register 0x0A01[5] = 1b), and the free run tuning word is set.
3. Write Register 0x0405 = 0x20.
4. Write Register 0x0005 = 0x01.
5. Write Register 0x0405 = 0x21.
6. Write Register 0x0005 = 0x01.
Monitor the APLL status using Bit 2 in Register 0x0D01.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9559 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual PLL, Quad Input, Multiservice Line Card Adaptive Clock Translator |
| AD9559/PCBZ | 功能描述:時鐘和定時器開發(fā)工具 Multi-protocol line card dual clock RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Modules 類型:Clock Conditioners 工具用于評估:LMK04100B 頻率:122.8 MHz 工作電源電壓:3.3 V |
| AD9559BCPZ | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 Multi-protocol line card dual clock RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| AD9559BCPZ-REEL7 | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 Multi-protocol line card dual clock RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| AD9559PCBZ | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual PLL, Quad Input, Multiservice Line Card Adaptive Clock Translator |
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