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參數(shù)資料
| 型號(hào)： | AD9558/PCBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 45/104頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD9558 |
| 產(chǎn)品變化通告： | AD9558 Minor Metal Mask Change 17/Apr/2012 |
| 設(shè)計(jì)資源： | AD9558 Eval Brd BOM AD9558 Schematic |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | * |
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Data Sheet
AD9558
Rev. B | Page 45 of 104
A pause instruction, like an end instruction, is stored at the
end of a sequence of instructions in the scratch pad. When the
controller encounters a pause instruction during an upload
sequence, it keeps the EEPROM address pointer at its last value.
This way the user can store a new instruction sequence in the
scratch pad and upload the new sequence to the EEPROM. The
new sequence is stored in the EEPROM address locations
immediately following the previously saved sequence. This
process is repeatable until an upload sequence contains an end
instruction. The pause instruction is also useful when used in
conjunction with condition processing. It allows the EEPROM
to contain multiple occurrences of the same registers, with each
occurrence linked to a set of conditions (see the EEPROM
Conditional Processing section).
EEPROM Upload
To upload data to the EEPROM, the user must first ensure that
the write enable bit (Register 0x0E00, Bit 0) is set. Then, on
setting the autoclearing save to EEPROM bit (Register 0x0E02,
Bit 0), the controller initiates the EEPROM data storage process.
Uploading EEPROM data requires that the user first write an
instruction sequence into the scratch pad registers. During the
upload process, the controller reads the scratch pad data byte-
by-byte, starting at Register 0x0E10 and incrementing the scratch
pad address pointer, as it goes, until it reaches a pause or end
instruction.
As the controller reads the scratch pad data, it transfers the
data from the scratch pad to the EEPROM (byte-by-byte) and
increments the EEPROM address pointer accordingly, unless
it encounters a data instruction. A data instruction tells the
controller to transfer data from the device settings portion of
the register map to the EEPROM. The number of bytes to transfer
is encoded within the data instruction, and the starting address
for the transfer appears in the next two bytes in the scratch pad.
When the controller encounters a data instruction, it stores the
instruction in the EEPROM, increments the EEPROM address
pointer, decodes the number of bytes to be transferred, and
increments the scratch pad address pointer. Then it retrieves the
next two bytes from the scratch pad (the target address) and
increments the scratch pad address pointer by 2. Next, the
controller transfers the specified number of bytes from the
register map (beginning at the target address) to the EEPROM.
When it completes the data transfer, the controller stores an extra
byte in the EEPROM to serve as a checksum for the transferred
block of data. To account for the checksum byte, the controller
increments the EEPROM address pointer by one more than the
number of bytes transferred. Note that, when the controller
transfers data associated with an active register, it actually
transfers the buffered contents of the register (refer to the
Buffered/Active Registers section for details on the difference
between buffered and active registers). This allows for the transfer
of nonzero autoclearing register contents.
Note that conditional processing (see the EEPROM Conditional
Processing section) does not occur during an upload sequence.
EEPROM Download
An EEPROM download results in data transfer from the
EEPROM to the device register map. To download data,
the user sets the autoclearing load from the EEPROM bit
(Register 0x0E03, Bit 1). This commands the controller to
initiate the EEPROM download process. During download, the
controller reads the EEPROM data byte-by-byte, incrementing
the EEPROM address pointer as it goes, until it reaches an end
instruction. As the controller reads the EEPROM data, it
executes the stored instructions, which includes transferring
stored data to the device settings portion of the register map
when it encounters a data instruction.
Note that conditional processing (see the EEPROM Conditional
Processing section) is applicable only when downloading.
Automatic EEPROM Download
Following a power-up, an assertion of the RESET pin, or a soft
reset (Register 0x0000, Bit 5 = 1), if the PINCONTROL pin is
low, and M3 and M2 are either high or low (see Table 22), the
instruction sequence stored in the EEPROM executes automatically
with one of eight conditions. If M3 and M2 are left floating and
the PINCONTROL pin is low, the EEPROM is bypassed and
the factory defaults are used. In this way, a previously stored set
of register values downloads automatically on power-up or with
a hard or soft reset. See the EEPROM Conditional Processing
section for details regarding conditional processing and the way
it modifies the download process.
Table 22. EEPROM Setup
M3
M2
ID
EEPROM Download?
Low
1
Yes, EEPROM Condition 1
Low
Open
2
Yes, EEPROM Condition 2
Low
High
3
Yes, EEPROM Condition 3
Open
Low
4
Yes, EEPROM Condition 4
Open
0
No
Open
High
5
Yes, EEPROM Condition 5
High
Low
6
Yes, EEPROM Condition 6
High
Open
7
Yes, EEPROM Condition 7
High
8
Yes, EEPROM Condition 8
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| AD9559 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual PLL, Quad Input, Multiservice Line Card Adaptive Clock Translator |
| AD9559/PCBZ | 功能描述:時(shí)鐘和定時(shí)器開發(fā)工具 Multi-protocol line card dual clock RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Modules 類型:Clock Conditioners 工具用于評(píng)估:LMK04100B 頻率:122.8 MHz 工作電源電壓:3.3 V |
| AD9559BCPZ | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 Multi-protocol line card dual clock RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| AD9559BCPZ-REEL7 | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 Multi-protocol line card dual clock RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
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