參數資料
型號： AD9558/PCBZ
廠商： Analog Devices Inc
文件頁數： 68/104頁
文件大?。?/td> 0K
描述： BOARD EVAL FOR AD9558
產品變化通告： AD9558 Minor Metal Mask Change 17/Apr/2012
設計資源： AD9558 Eval Brd BOM
AD9558 Schematic
標準包裝： 1
系列： *
AD9558
Data Sheet
Rev. B | Page 66 of 104
Reg
Addr
(Hex)
Opt
Name
D7
D6
D5
D4
D3
D2
D1
D0
Def
Profile B (for REFB)
0x0740
L
Reference
period (up to
1.1 ms)
Nominal period (fs), Bits[7:0] (default: 125 s = 1/(8 kHz) for default system clock setting)
00
0x0741
L
Nominal period (fs), Bits[15:8]
A2
0x0742
L
Nominal period (fs), Bits[23:16]
94
0x0743
L
Nominal period (fs), Bits[31:24]
1A
0x0744
L
Nominal period (fs), Bits[39:32]
1D
0x0745
L
Frequency
tolerance
Inner tolerance (1 ppm), Bits[7:0] (for reference invalid to valid; 50% down to 1 ppm) (default: 5%)
14
0x0746
L
Inner tolerance (1 ppm), Bits[15:8] (for reference invalid to valid; 50% down to 1 ppm)
00
0x0747
L
Reserved
Inner tolerance, Bits[19:16]
00
0x0748
L
Outer tolerance (1 ppm), Bits[7:0] (for reference valid to invalid; 50% down to 1 ppm] (default: 10%)
0A
0x0749
L
Outer tolerance (1 ppm), Bits[15:8] (for reference valid to invalid; 50% down to 1 ppm)
00
0x074A
L
Reserved
Outer tolerance, Bits[19:16]
00
0x074B
L
Validation
Validation timer (ms), Bits[7:0] (up to 65.5 seconds)
0A
0x074C
L
Validation timer (ms), Bits[15:8] (up to 65.5 seconds)
00
0x074D
L
Reserved
00
0x074E
L
Select base
loop filter
Reserved
Sel high PM
base loop
filter
00
0x074F
L
DPLL loop BW
Digital PLL loop BW scaling factor[7:0] (default: 0x01F4 = 50 Hz)
F4
0x0750
L
Digital PLL loop BW scaling factor[15:8]
01
0x0751
L
Reserved
BW scaling
factor[16]
00
0x0752
L
DPLL
R divider
(20 bits)
R divider[7:0]
00
0x0753
L
R divider[15:8]
00
0x0754
L
Reserved
Enable REFB
divide-by-2
R divider[19:16]
00
0x0755
DPLL
N divider
(17 bits)
Digital PLL feedback divider—Integer Part N1[7:0]
1F
0x0756
Digital PLL feedback divider—Integer Part N1[15:8]
5B
0x0757
Reserved
Digital PLL
feedback
divider—
Integer Part
N1[16]
00
0x0758
DPLL
fractional
feedback
divider
(24 bits)
Digital PLL fractional feedback divider—FRAC1[7:0]
00
0x0759
Digital PLL fractional feedback divider—FRAC1[15:8]
00
0x075A
Digital PLL fractional feedback divider—FRAC1[23:16]
00
0x075B
DPLL
fractional
feedback
divider
modulus
(24 bits)
Digital PLL feedback divider modulus—MOD1[7:0]
01
0x075C
Digital PLL feedback divider modulus—MOD1[15:8]
00
0x075D
Digital PLL feedback divider modulus—MOD1[23:16]
00
0x075E
L
Lock detectors
Phase lock threshold (ps), Bits[7:0]
BC
0x075F
L
Phase lock threshold(ps), Bits[15:8]
02
0x0760
L
Phase lock fill rate[7:0]
0A
0x0761
L
Phase lock drain rate[7:0]
0A
0x0762
L
Frequency lock threshold[7:0]
BC
0x0763
L
Frequency lock threshold[15:8]
02
0x0764
L
Frequency lock threshold[23:16]
00
0x0765
L
Frequency lock fill rate[7:0]
0A
0x0766
L
Frequency lock drain rate[7:0]
0A
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相關代理商/技術參數
參數描述
AD9559 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual PLL, Quad Input, Multiservice Line Card Adaptive Clock Translator
AD9559/PCBZ 功能描述:時鐘和定時器開發(fā)工具 Multi-protocol line card dual clock RoHS:否 制造商:Texas Instruments 產品:Evaluation Modules 類型:Clock Conditioners 工具用于評估:LMK04100B 頻率:122.8 MHz 工作電源電壓:3.3 V
AD9559BCPZ 功能描述:時鐘發(fā)生器及支持產品 Multi-protocol line card dual clock RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56
AD9559BCPZ-REEL7 功能描述:時鐘發(fā)生器及支持產品 Multi-protocol line card dual clock RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56
AD9559PCBZ 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual PLL, Quad Input, Multiservice Line Card Adaptive Clock Translator
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