參數(shù)資料
型號(hào): AD9558/PCBZ
廠商: Analog Devices Inc
文件頁數(shù): 20/104頁
文件大小: 0K
描述: BOARD EVAL FOR AD9558
產(chǎn)品變化通告: AD9558 Minor Metal Mask Change 17/Apr/2012
設(shè)計(jì)資源: AD9558 Eval Brd BOM
AD9558 Schematic
標(biāo)準(zhǔn)包裝: 1
系列: *
AD9558
Data Sheet
Rev. B | Page 22 of 104
–160
–150
–140
–130
–120
–110
–100
–90
–80
–70
1k
10
100
10k
100k
1M
10M
100M
PH
A
SE
N
O
ISE
(d
B
c
/H
z)
FREQUENCY OFFSET (Hz)
INTEGRATED RMS JITTER (12kHz TO 20MHz): 391fs
09758-
013
Figure 13. Absolute Phase Noise (Output Driver = 3.3 V CMOS),
fR = 19.44 MHz, fOUT =161.1328125 MHz,
DPLL Loop BW = 0.1 Hz, fSYS = 19.2 MHz TCXO
–160
–150
–140
–130
–120
–110
–100
–90
–80
–70
1k
10
100
10k
100k
1M
10M
100M
PH
A
SE
N
O
ISE
(d
B
c
/H
z)
FREQUENCY OFFSET (Hz)
INTEGRATED RMS JITTER (12kHz TO 20MHz): 395fs
09758-
014
Figure 14. Absolute Phase Noise (Output Driver = 1.8 V CMOS),
fR = 2 kHz, fOUT = 70.656 MHz,
DPLL Loop BW = 0.1 Hz, fSYS = 19.2 MHz TCXO
1k
10
100
10k
100k
1M
10M
100M
–160
–150
–140
–130
–120
–110
–100
–90
–80
–70
–60
PH
A
SE
N
O
ISE
(d
B
c
/H
z)
FREQUENCY OFFSET (Hz)
INTEGRATED RMS JITTER (12kHz TO 20MHz): 388fs
09758-
016
Figure 15. Absolute Phase Noise (Output Driver = HSTL),
fR = 19.44 MHz, fOUT = 644.53 MHz, fSYS = 19.2 MHz TCXO
Holdover Mode
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
D
IFFE
R
E
N
TIA
L
P
E
AK-
T
O
-PEA
K
A
MPL
IT
U
D
E
(V)
0
100
200
300
400
500
600
700
800
900
1000
1
100
1200
1300
FREQUENCY (MHz)
09758-
1
16
Figure 16. Amplitude vs. Toggle Rate,
HSTL Mode (LVPECL-Compatible Mode)
0.4
0.5
0.6
0.7
0.8
0.9
1.0
0
100
200
300
400
500
600
700
800
D
IFFE
R
E
N
TIA
L
P
E
AK-
T
O
-PEA
K
A
MPL
IT
U
D
E
(V)
FREQUENCY (MHz)
LVDS BOOST MODE
LVDS DEFAULT
09758-
1
17
Figure 17. Amplitude vs. Toggle Rate, LVDS
1.0
1.5
2.0
2.5
3.0
3.5
0
50
100
150
200
250
300
P
E
AK-
T
O
-PEA
K
A
MPL
IT
U
D
E
(V)
FREQUENCY (MHz)
3.3V CMOS
1.8V CMOS
09758-
1
18
Figure 18. Amplitude vs. Toggle Rate with 10 pF Load,
3.3 V (Strong Mode) and 1.8 V CMOS
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