參數(shù)資料
型號(hào)： AD9558/PCBZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 90/104頁(yè)
文件大小： 0K
描述： BOARD EVAL FOR AD9558
產(chǎn)品變化通告： AD9558 Minor Metal Mask Change 17/Apr/2012
設(shè)計(jì)資源： AD9558 Eval Brd BOM
AD9558 Schematic
標(biāo)準(zhǔn)包裝： 1
系列： *
AD9558
Data Sheet
Rev. B | Page 86 of 104
FRAME SYNCHRONIZATION (REGISTER 0x0640 TO REGISTER 0x0641)
Table 77. Frame Sync Setting
Address
Bit(s)
Bit Name
Description
0x0640
[7:1]
Reserved
Reserved; default: 0x00.
0
Enable Fsync
Enable frame synchronization.
0 (default) = frame synchronization disabled.
1 = frame synchronization enabled.
0x0641
[7:4]
Reserved
Reserved; default: 0x00.
3
Validate Fsync ref
Setting this bit forces the reference validation logic to declare REFA valid only if the
REFB (the sync pulse) input is also valid. This bit can be thought as a logical AND of
REFA VALID and REFB VALID signals. If REFC is selected, this bit requires that REFD
(the sync pulse) input also be valid before declaring REFC valid.
0 (default) = only the selected reference input must be valid.
1 = the sync pulse input must also be valid to validate the selected input.
2
Fsync one shot
Selects one-shot or level-sensitive frame sync function.
0 (default) = use level-sensitive frame sync. Frame sync occurs on every edge of the
frame pulse.
1 = use one-shot frame sync. Frame sync occurs only on the first frame sync pulse
(on REFB or REFD). User must re-arm by raising the SYNC pin high and then low, or
by clearing and resetting the arm soft Fsync bit. As with all buffered registers, an
I/O update is required (Register 0x0005[0] = 0x01) after writing this register.
1
Fsync arm method
Selects which signal is used to arm the frame sync
0 (default) = use SYNC pin.
1 = use arm soft Fsync (Register 0x0641[0]).
0
Arm soft Fsync
Arms frame sync after I/O update. Next pulse on REFB or REFD is the sync pulse. The
Fsync arm method bit must also be set for this bit to take effect.
0 = (default); frame sync unarmed.
1 = frame sync armed.
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AD9559 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual PLL, Quad Input, Multiservice Line Card Adaptive Clock Translator
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AD9559BCPZ 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 Multi-protocol line card dual clock RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56
AD9559BCPZ-REEL7 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 Multi-protocol line card dual clock RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56
AD9559PCBZ 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual PLL, Quad Input, Multiservice Line Card Adaptive Clock Translator
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