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| 型號： | AD9558/PCBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 78/104頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD9558 |
| 產(chǎn)品變化通告： | AD9558 Minor Metal Mask Change 17/Apr/2012 |
| 設計資源： | AD9558 Eval Brd BOM AD9558 Schematic |
| 標準包裝： | 1 |
| 系列： | * |
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Data Sheet
AD9558
Rev. B | Page 75 of 104
IRQ MASK (REGISTER 0x020A TO REGISTER 0x020F)
The IRQ mask register bits form a one-to-one correspondence with the bits of the IRQ monitor register (0x0D02 to 0x0D09). When set to
Logic 1, the IRQ mask bits enable the corresponding IRQ monitor bits to indicate an IRQ event. The default for all IRQ mask bits is Logic 0,
which prevents the IRQ monitor from detecting any internal interrupts.
Table 48. IRQ Mask for SYSCLK
Address
Bits
Bit Name
Description
0x020A
[7:6]
Reserved
5
SYSCLK unlocked
Enables IRQ for indicating a SYSCLK PLL state transition from locked to unlocked
4
SYSCLK locked
Enables IRQ for indicating a SYSCLK PLL state transition from unlocked to locked
3
APLL unlocked
Enables IRQ for indicating an APLL state transition from locked to unlocked
2
APLL locked
Enables IRQ for indicating an APLL state transition from unlocked to locked
1
APLL cal complete
Enables IRQ for indicating that APLL (LCVCO) calibration has completed
0
APLL cal started
Enables IRQ for indicating that APLL (LCVCO) calibration has begun
Table 49. IRQ Mask for Distribution Sync, Watchdog Timer, and EEPROM
Address
Bits
Bit Name
Description
0x020B
[7:5]
Reserved
4
Pin program end
Enables IRQ for indicating successful completion of a pin program ROM load
3
Sync distribution
Enables IRQ for indicating a distribution sync event
2
Watchdog timer
Enables IRQ for indicating expiration of the watchdog timer
1
EEPROM fault
Enables IRQ for indicating a fault during an EEPROM load or save operation
0
EEPROM complete
Enables IRQ for indicating successful completion of an EEPROM load or save operation
Table 50. IRQ Mask for the Digital PLL
Address
Bits
Bit Name
Description
0x020C
7
Switching
Enables IRQ for indicating that the DPLL is switching to a new reference
6
Closed
Enables IRQ for indicating that the DPLL has entered closed-loop operation
5
Freerun
Enables IRQ for indicating that the DPLL has entered free run mode
4
Holdover
Enables IRQ for indicating that the DPLL has entered holdover mode
3
Frequency unlocked
Enables IRQ for indicating that the DPLL lost frequency lock
2
Frequency locked
Enables IRQ for indicating that the DPLL has acquired frequency lock
1
Phase unlocked
Enables IRQ for indicating that the DPLL lost phase lock
0
Phase locked
Enables IRQ for indicating that the DPLL has acquired phase lock
Table 51. IRQ Mask for History Update, Frequency Limit and Phase Slew Limit
Address
Bits
Bit Name
Description
0x020D
[7:5]
Reserved
4
History updated
Enables IRQ for indicating the occurrence of a tuning word history update
3
Frequency unclamped
Enables IRQ for indicating a frequency limit state transition from clamped to unclamped
2
Frequency clamped
Enables IRQ for indicating a state transition of the frequency limiter from unclamped to clamped
1
Phase slew unlimited
Enables IRQ for indicating a state transition of the phase slew limiter from slew limiting to not
slew limiting
0
Phase slew limited
Enables IRQ for indicating a state transition of the phase slew limiter from not slew limiting to
slew limiting
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AD9559 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual PLL, Quad Input, Multiservice Line Card Adaptive Clock Translator |
| AD9559/PCBZ | 功能描述:時鐘和定時器開發(fā)工具 Multi-protocol line card dual clock RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Modules 類型:Clock Conditioners 工具用于評估:LMK04100B 頻率:122.8 MHz 工作電源電壓:3.3 V |
| AD9559BCPZ | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 Multi-protocol line card dual clock RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| AD9559BCPZ-REEL7 | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 Multi-protocol line card dual clock RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| AD9559PCBZ | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual PLL, Quad Input, Multiservice Line Card Adaptive Clock Translator |
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