參數(shù)資料
型號: AD9558/PCBZ
廠商: Analog Devices Inc
文件頁數(shù): 14/104頁
文件大?。?/td> 0K
描述: BOARD EVAL FOR AD9558
產(chǎn)品變化通告: AD9558 Minor Metal Mask Change 17/Apr/2012
設(shè)計資源: AD9558 Eval Brd BOM
AD9558 Schematic
標準包裝: 1
系列: *
Data Sheet
AD9558
Rev. B | Page 17 of 104
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
NOTES
1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.
2. THE EXPOSED PAD MUST BE CONNECTED TO GROUND (VSS).
09758-
002
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
A
V
DD
OU
T2
OU
T2
OU
T1
OU
T1
A
V
DD
OU
T5
OU
T5
A
V
DD3
A
V
DD3
OU
T0
OU
T0
A
V
DD
A
V
DD
A
V
DD3
L
DO
_V
CO
2
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
DV
DD3
M6
M5
M4
M3
M2
M1
M0
DV
DD
DV
DD
RE
F
B
RE
F
B
DV
DD3
DV
DD3
RE
F
D
RE
F
D
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
IRQ
SCLK/SCL
SDIO/SDA
SDO
CS
DVDD
AVDD
XOA
XOB
AVDD
NC
AVDD
OUT4
OUT3
REFC
DVDD3
REFA
SYNC
M7
PINCONTROL
RESET
AVDD
NC
AVDD
NC
LF_VCO2
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
AD9558
TOP VIEW
(Not to Scale)
PIN 1
INDICATOR
Figure 2. Pin Configuration
Table 20. Pin Function Descriptions
Pin No.
Mnemonic
Input/
Output
Pin Type
Description
1
IRQ
O
3.3 V CMOS
Interrupt Request Line.
2
SCLK/SCL
I
3.3 V CMOS
Serial Programming Clock (SCLK) in SPI Mode. Data clock for serial programming.
Open-Collector Serial Clock Pin (SCL) in I2C Mode. Requires a pull-up resistor, usually
2.2 k; the resistor size depends on the number of I2C devices on the bus.
3
SDIO/SDA
I/O
3.3 V CMOS
Serial Data Input/Output (SDIO) in SPI Mode. When the device is in 4-wire SPI mode,
data is written via this pin. In 3-wire SPI mode, both data reads and writes occur on
this pin. There is no internal pull-up/pull-down resistor on this pin.
Open-Collector Serial Data Pin (SDA) in I2C Mode. Requires a pull-up resistor, usually
2.2 k; the resistor size depends on the number of I2C devices on the bus.
4
SDO
O
3.3 V CMOS
Serial Data Output. Use this pin to read data in 4-wire mode. There is no internal pull-up/
pull-down resistor on this pin. This pin is high impedance in the default 3-wire mode.
5
AA
CSEE
I
3.3 V CMOS
Chip Select (SPI), Active Low. When programming a device, this pin must be held low.
In systems where more than one AD9558 is present, this pin enables individual
programming of each AD9558. This pin has an internal 10 k pull-up resistor.
6, 55, 56
DVDD
I
Power
1.8 V Digital Supply.
7
AVDD
I
Power
1.8 V Analog (SYSCLK) Power Supply.
8
XOA
I
Differential
input
System Clock Input. XOA contains internal dc biasing and should be ac-coupled with
a 0.01 μF capacitor, except when using a crystal. If a crystal is used, connect the crystal
across XOA and XOB. Single-ended 1.8 V CMOS is also an option but can introduce
a spur if the duty cycle is not 50%. When using XOA as a single-ended input, connect
a 0.01 μF capacitor from XOB to ground.
9
XOB
I
Differential
input
Complementary System Clock Input. Complementary signal to XOA. XOB contains
internal dc biasing and should be ac-coupled with a 0.01 μF capacitor, except when
using a crystal. If a crystal is used, connect the crystal across XOA and XOB.
10
AVDD
I
Power
1.8 V Analog (VCO) Power Supply.
11
NC
I
No Connection. Do not connect to this pin.
12, 17,
22, 29,
30
AVDD
I
Power
1.8 V Analog (Output Driver) Power Supply.
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