參數(shù)資料
型號(hào)： AD9558/PCBZ
廠商： Analog Devices Inc
文件頁數(shù)： 76/104頁
文件大?。?/td> 0K
描述： BOARD EVAL FOR AD9558
產(chǎn)品變化通告： AD9558 Minor Metal Mask Change 17/Apr/2012
設(shè)計(jì)資源： AD9558 Eval Brd BOM
AD9558 Schematic
標(biāo)準(zhǔn)包裝： 1
系列： *
Data Sheet
AD9558
Rev. B | Page 73 of 104
SYSTEM CLOCK (REGISTER 0x0100 TO REGISTER 0x0108)
Table 42. System Clock PLL Feedback Divider (N3 Divider)
Address
Bits
Bit Name
Description
0x0100
[7:0]
SYSCLK N3 divider
System clock PLL feedback divider value: 4 ≤ N3 ≤ 255 (default: 0x08).
Table 43. SYSCLK Configuration
Address
Bits
Bit Name
Description
0x0101
[7:5]
Reserved
Reserved.
4
Load from ROM
(read-only)
This read-only bit is set if the PINCONTROL pin was high during the last power-on.
0 = The PINCONTROL pin was low at power-on (or reset).
1 = The PINCONTROL pin was high at power-on (or reset).
3
SYSCLK XTAL enable
Enables the crystal maintaining amplifier for the system clock input.
1 (default) = crystal mode (crystal maintaining amplifier enabled).
0 = external XO or other system clock source.
[2:1]
SYSCLK P divider
System clock input divider.
00 (default) = 1.
01 = 2.
10 = 4.
11 = 8.
0
SYSCLK doubler enable
Enable clock doubler on system clock input to reduce noise.
0 = disable.
1 (default) = enable.
Table 44. Nominal System Clock Period1
Address
Bits
Bit Name
Description
0x0103
[7:0]
Nominal system clock period (fs)
System clock period, Bits[7:0].
Default: 0x0E.
0x0104
[7:0]
System clock period, Bits[15:8].
Default: 0x67.
0x0105
[7:5]
Reserved
Reserved.
[4:0]
Nominal system clock period (fs)
System clock period, Bits[20:16].
Default: 0x13.
1
Note that the default setting for system clock period is 1.271566 ns, which is the period of 786.432 MHz (= 49.152 MHz × 16).
Table 45. System Clock Stability Period
Address
Bits
Bit Name
Description
0x0106
[7:0]
System clock stability period (ms)
System clock period, Bits[7:0].
Default: 0x32 (0x000032 = 50 ms).
0x0107
[7:0]
System clock period, Bits[15:8].
Default: 0x00.
0x0108
[7:5]
Reserved
Reserved.
4
Reset SYSCLK stability timer
This autoclearing bit resets the system clock stability timer.
[3:0]
System clock stability period
System clock period, Bits[19:16].
Default: 0x00.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD9559 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual PLL, Quad Input, Multiservice Line Card Adaptive Clock Translator
AD9559/PCBZ 功能描述:時(shí)鐘和定時(shí)器開發(fā)工具 Multi-protocol line card dual clock RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Modules 類型:Clock Conditioners 工具用于評估:LMK04100B 頻率:122.8 MHz 工作電源電壓:3.3 V
AD9559BCPZ 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 Multi-protocol line card dual clock RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56
AD9559BCPZ-REEL7 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 Multi-protocol line card dual clock RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56
AD9559PCBZ 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual PLL, Quad Input, Multiservice Line Card Adaptive Clock Translator
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