參數(shù)資料
型號： AD9558/PCBZ
廠商： Analog Devices Inc
文件頁數(shù)： 5/104頁
文件大?。?/td> 0K
描述： BOARD EVAL FOR AD9558
產(chǎn)品變化通告： AD9558 Minor Metal Mask Change 17/Apr/2012
設(shè)計資源： AD9558 Eval Brd BOM
AD9558 Schematic
標(biāo)準(zhǔn)包裝： 1
系列： *
AD9558
Data Sheet
Rev. B | Page 102 of 104
Table 129. Multifunction Pin Output Functions (D7 = 1)
Register Value
Output Function
Equivalent Status Register
0x80
Static Logic 0
None
0x81
Static Logic 1
None
0x82
System clock divided by 32
None
0x83
Watchdog timer output
None
0x84
EEPROM upload in progress
Register 0x0D00, Bit 0
0x85
EEPROM download in progress
Register 0x0D00, Bit 1
0x86
EEPROM fault detected
Register 0x0D00, Bit 2
0x87
SYSCLK PLL lock detected
Register 0x0D01, Bit 0
0x88
SYSCLK PLL stable
Register 0x0D01, Bit 1
0x89
Output PLL locked
Register 0x0D01, Bit 2
0x8A
APLL calibration in process
Register 0x0D01, Bit 3
0x8B
APLL input reference present
Register 0x0D01, Bit 4
0x8C
All PLLs locked
Register 0x0D01, Bit 5
(DPLL phase lock) and (APLL lock) and (sys PLL lock)
0x8D
(DPLL phase lock) and (APLL lock)
Register 0x0D01, Bit 6
0x8E
Reserved
0x8F
Reserved
0x90
DPLL free run
Register 0x0D08, Bit 0
0x91
DPLL active
Register 0x0D08, Bit 1
0x92
DPLL in holdover
Register 0x0D08, Bit 2
0x93
DPLL in reference switchover
Register 0x0D08, Bit 3
0x94
DPLL phase locked
Register 0x0D08, Bit 4
0x95
DPLL frequency locked
Register 0x0D08, Bit 5
0x96
DPLL phase slew limited
Register 0x0D08, Bit 6
0x97
DPLL frequency clamped
Register 0x0D09, Bit 5
0x98
Tuning word history available
Register 0x0D09, Bit 4
0x99
Tuning word history updated
Register 0x0D05, Bit 4
0x9A to 0x9F
Reserved
0xA0
Reference A fault
Register 0x0D0B, Bit 2
0xA1
Reference B fault
Register 0x0D0B, Bit 6
0xA2
Reference C fault
Register 0x0D0C, Bit 2
0xA3
Reference D fault
Register 0x0D0C, Bit 6
0xA4 to Ax2F
Reserved
0xB0
Reference A valid
Register 0x0D0B, Bit 3
0xB1
Reference B valid
Register 0x0D0B, Bit 7
0xB2
Reference C valid
Register 0x0D0C, Bit 3
0xB3
Reference D valid
Register 0x0D0C, Bit 7
0xB4 to 0xBF
Reserved
0xC0
Reference A active
Register 0x0D09, Bits[1:0]
0xC1
Reference B active
Register 0x0D09, Bits[1:0]
0xC2
Reference C active
Register 0x0D09, Bits[1:0]
0xC3
Reference D active
Register 0x0D09, Bits[1:0]
0xC4 to 0xCF
Reserved
0xD0
Clock distribution sync pulse
Register 0x0D03, Bit 3
0xD1
Soft pin configuration in progress
Register 0x0D03, Bit 4
0xD2 to 0FF
Reserved
相關(guān)PDF資料
PDF描述
GBM22DSAH CONN EDGECARD 44POS R/A .156 SLD
DK-2632-03 CABLE FIBER OPTIC DUAL LC-SC 3M
GEM30DTAS CONN EDGECARD 60POS R/A .156 SLD
GMM12DRXI CONN EDGECARD 24POS DIP .156 SLD
P1330R-105K INDUCTOR POWER 1000.0UH SMD
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD9559 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual PLL, Quad Input, Multiservice Line Card Adaptive Clock Translator
AD9559/PCBZ 功能描述:時鐘和定時器開發(fā)工具 Multi-protocol line card dual clock RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Modules 類型:Clock Conditioners 工具用于評估:LMK04100B 頻率:122.8 MHz 工作電源電壓:3.3 V
AD9559BCPZ 功能描述:時鐘發(fā)生器及支持產(chǎn)品 Multi-protocol line card dual clock RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56
AD9559BCPZ-REEL7 功能描述:時鐘發(fā)生器及支持產(chǎn)品 Multi-protocol line card dual clock RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56
AD9559PCBZ 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual PLL, Quad Input, Multiservice Line Card Adaptive Clock Translator
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*