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參數(shù)資料
| 型號： | AD9558/PCBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 85/104頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR AD9558 |
| 產(chǎn)品變化通告： | AD9558 Minor Metal Mask Change 17/Apr/2012 |
| 設(shè)計資源： | AD9558 Eval Brd BOM AD9558 Schematic |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | * |
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Data Sheet
AD9558
Rev. B | Page 81 of 104
OUTPUT CLOCK DISTRIBUTION (REGISTER 0x0500 TO REGISTER 0x0515)
Table 67. Clock Distribution Output Synchronization Settings
Address
Bits
Bit Name
Description
0x0500
7
Mask Channel 3 sync
Masks the synchronous reset to the Channel 3 (M3) divider.
0 (default) = unmasked. The output drivers do not toggle until a SYNC pulse occurs.
1 = masked. Setting this bit asynchronously releases Channel 3 from the static SYNC state,
thus allowing the Channel 3 divider to toggle. Channel 3 ignores all SYNC events while
this bit is set. Setting this bit does not enable the output drivers connected to this channel. In
addition, the output distribution sync also depends on the setting of Register 0x0405[3].
6
Mask Channel 2 sync
Masks the synchronous reset to the Channel 2 (M2) divider.
0 (default) = unmasked. The output drivers do not toggle until a SYNC pulse occurs.
1 = masked. Setting this bit asynchronously releases Channel 2 from the static SYNC state,
thus allowing the Channel 2 divider to toggle. Channel 2 ignores all SYNC events while
this bit is set. Setting this bit does not enable the output drivers connected to this channel. In
addition, the output distribution sync also depends on the setting of Register 0x0405[3].
5
Masks the synchronous reset to the Channel 1 (M2) divider.
0 (default) = unmasked. The output drivers do not toggle until a SYNC pulse occurs.
1 = masked. Setting this bit asynchronously releases Channel 1 from the static SYNC state,
thus allowing the Channel 1 divider to toggle. Channel 1 ignores all SYNC events while
this bit is set. Setting this bit does not enable the output drivers connected to this
channel. In addition, the output distribution sync also depends on the setting of Register
0x0405[3].
4
Mask Channel 0 sync
Masks the synchronous reset to the Channel 0 (M0) divider.
0 (default) = unmasked. The output drivers do not toggle until a SYNC pulse occurs.
1 = masked. Setting this bit asynchronously releases Channel 0 from the static SYNC state,
thus allowing the Channel 0 divider to toggle. Channel 0 ignores all SYNC events while
this bit is set. Setting this bit does not enable the output drivers connected to this channel. In
addition, the output distribution sync also depends on the setting of Register 0x0405[3].
3
Reserved
Default: 0b.
2
Sync source selection
Selects the sync source for the clock distribution output channels.
0 (default) = direct. The sync pulse happens on the next I/O update.
1 = active reference.
Note that the output distribution sync also depends on the APLL being calibrated and
locked unless Register 0x0405[3] = 1b.
[1:0]
Automatic sync mode
Autosync mode.
00 = disabled. A sync command must be issued manually, or by using the mask sync bits
in this register (Bits[7:4]).
01 = sync on DPLL frequency lock.
10 (default) = sync on DPLL phase lock.
11 = reserved.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9559 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual PLL, Quad Input, Multiservice Line Card Adaptive Clock Translator |
| AD9559/PCBZ | 功能描述:時鐘和定時器開發(fā)工具 Multi-protocol line card dual clock RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Modules 類型:Clock Conditioners 工具用于評估:LMK04100B 頻率:122.8 MHz 工作電源電壓:3.3 V |
| AD9559BCPZ | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 Multi-protocol line card dual clock RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| AD9559BCPZ-REEL7 | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 Multi-protocol line card dual clock RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| AD9559PCBZ | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual PLL, Quad Input, Multiservice Line Card Adaptive Clock Translator |
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