SERIAL PORT SPECIFICATIONS—I2C MODE Ta" />
參數(shù)資料
型號： AD9558/PCBZ
廠商： Analog Devices Inc
文件頁數(shù)： 10/104頁
文件大?。?/td> 0K
描述： BOARD EVAL FOR AD9558
產品變化通告： AD9558 Minor Metal Mask Change 17/Apr/2012
設計資源： AD9558 Eval Brd BOM
AD9558 Schematic
標準包裝： 1
系列： *
Data Sheet
AD9558
Rev. B | Page 13 of 104
SERIAL PORT SPECIFICATIONS—I2C MODE
Table 16.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
SDA, SCL (AS INPUT)
Input Logic 1 Voltage
0.7 ×
DVDD3
V
Input Logic 0 Voltage
0.3 ×
DVDD3
V
Input Current
10
+10
A
For VIN = 10% to 90% DVDD3
Hysteresis of Schmitt Trigger Inputs
0.015 ×
DVDD3
Pulse Width of Spikes That Must Be Suppressed by
the Input Filter, tSP
50
ns
SDA (AS OUTPUT)
Output Logic 0 Voltage
0.4
V
IO = 3 mA
Output Fall Time from VIHmin to VILmax
20 + 0.1 Cb
250
ns
10 pF ≤ Cb ≤ 400 pF
TIMING
SCL Clock Rate
400
kHz
Bus-Free Time Between a Stop and Start
Condition, tBUF
1.3
s
Repeated Start Condition Setup Time, tSU; STA
0.6
s
Repeated Hold Time Start Condition, tHD;STA
0.6
s
After this period, the first clock pulse is
generated
Stop Condition Setup Time, tSU; STO
0.6
s
Low Period of the SCL Clock, tLOW
1.3
s
High Period of the SCL Clock, tHIGH
0.6
s
SCL/SDA Rise Time, tR
20 + 0.1 Cb1
300
ns
SCL/SDA Fall Time, tF
20 + 0.1 Cb1
300
ns
Data Setup Time, tSU; DAT
100
ns
Data Hold Time, tHD; DAT
100
ns
Capacitive Load for Each Bus Line, Cb1
400
pF
1
Cb is the capacitance (pF) of a single bus line.
JITTER GENERATION
Jitter generation (random jitter) uses 49.152 MHz crystal for system clock input.
Table 17.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
JITTER GENERATION
System clock doubler enabled;
high phase margin mode enabled;
Register 0x0405 = 0x20; Register 0x0403 =
0x07; Register 0x0400 = 0x81;
in cases where multiple driver types are
listed, both driver types were tested at
those conditions, and the one with higher
jitter is quoted, although there is usually
not a significant jitter difference between
the driver types
fREF = 19.44 MHz; fOUT = 622.08 MHz; fLOOP = 50 Hz
HSTL Driver
Bandwidth: 5 kHz to 20 MHz
304
fs rms
Bandwidth: 12 kHz to 20 MHz
296
fs rms
Bandwidth: 20 kHz to 80 MHz
300
fs rms
Bandwidth: 50 kHz to 80 MHz
266
fs rms
Bandwidth: 16 MHz to 320 MHz
185
fs rms
相關PDF資料
PDF描述
GBM22DSAH CONN EDGECARD 44POS R/A .156 SLD
DK-2632-03 CABLE FIBER OPTIC DUAL LC-SC 3M
GEM30DTAS CONN EDGECARD 60POS R/A .156 SLD
GMM12DRXI CONN EDGECARD 24POS DIP .156 SLD
P1330R-105K INDUCTOR POWER 1000.0UH SMD
相關代理商/技術參數(shù)
參數(shù)描述
AD9559 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual PLL, Quad Input, Multiservice Line Card Adaptive Clock Translator
AD9559/PCBZ 功能描述:時鐘和定時器開發(fā)工具 Multi-protocol line card dual clock RoHS:否 制造商:Texas Instruments 產品:Evaluation Modules 類型:Clock Conditioners 工具用于評估:LMK04100B 頻率:122.8 MHz 工作電源電壓:3.3 V
AD9559BCPZ 功能描述:時鐘發(fā)生器及支持產品 Multi-protocol line card dual clock RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56
AD9559BCPZ-REEL7 功能描述:時鐘發(fā)生器及支持產品 Multi-protocol line card dual clock RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56
AD9559PCBZ 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual PLL, Quad Input, Multiservice Line Card Adaptive Clock Translator
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*