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參數(shù)資料
| 型號： | MB86964PFV-G |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100 |
| 封裝： | SHRINK, PLASTIC, QFP-100 |
| 文件頁數(shù)： | 7/52頁 |
| 文件大?。?/td> | 373K |
| 代理商： | MB86964PFV-G |
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MB86964
15
PREAMBLE
LENGTH
DESTINATION
ADDRESS
SOURCE
ADDRESS
DATA
CRC
86
6
2
4
46-1500
LENGTHS SHOWN IN BYTES
Figure 10. Packet Format
Backoff Generator
A 17-bit pseudo-random number generator clocked at the 10
MHz bit rate provides the collision backoff function. Distances
between stations become part of the randomizing function.
The number generator is sampled at the time of collision, mask-
ing all but the appropriate number of bits specified by the
8802-3 backoff algorithm. This value is then counted down at
the slot-time rate (512 bit times) to generate the backoff inter-
val. For a first collision, only one bit is used, giving a backoff of
either 51.2 microseconds or 0. For a second consecutive colli-
sion, two bits are used, and so forth, up to ten bits. From the
tenth to the 16th collisions, 10 bits are used. This generates a
pseudo-random backoff interval of from 0 to 52.38 ms, the so-
called ’binary exponential backoff’ for collisions per the
8802-3 standard.
Transmit Error Processing
The MB86964 provides four transmit error status bits in its
Transmit Status Register (DLCR0) for reporting the four pos-
sible transmit errors. The errors are: 1) loss of carrier during
transmission, which usually indicates a medium fault or a colli-
sion, 2) collision, 3) 16 consecutive collisions and 4) jabber er-
ror, which occurs if the length of a single transmission substan-
tially exceeds the time required to transmit a maximum length
packet conforming to the standard. The latter three can be en-
abled separately to generate interrupts.
A status bit in the Transmit Status Register is set in case a colli-
sion terminates transmission. Collision counter DLCR4<7:4>,
automatically increments after each collision up to the six-
teenth collision, at which time it rolls over to zero. Another sta-
tus bit indicates that sixteen consecutive attempts to transmit a
packet have been made and all have been terminated by colli-
sion. The occurrence of 16 collisions may indicate a network
problem, such as a disconnected cable or terminator, that pro-
duces false collisions. While rare, 16 collisions may normally
occur.
Time Domain Reflectometry
When a node transmits, a short or open on the network causes a
reflected signal to the node receiver, which can sometimes be
detected. The reflection causes failure of the carrier sense or
detection of a false collision. An open on the network may
cause a false collision, whereas a short usually causes loss of
carrier sense. Time domain reflectometry (TDR) allows esti-
mates of the distance along the network cable from the node to
the fault.
The MB86964 is equipped with a special counter to perform
the TDR function. The contents of the counter after any trans-
mission can be determined by reading the Time Domain Re-
flectometry registers, DLCR14 (the least-significant byte) and
DLCR15 (the most-significant byte). Only the lower 14 bits of
the counter are equipped, which is more than is needed for an
IEEE or Ethernet LAN. The top two bits, DLCR15<7:6>, are
always 0. The TDR counter counts the actual number of bits
transmitted for each packet before a collision indication, carri-
er loss indication or completion of transmission, whichever
comes first. A complete transmission with no error indications
clears the TDR counter. The elapsed time represents twice the
signal delay from node to fault.
To perform the TDR fault test, first enable interrupts for TX
DONE, by setting DLCR2<7> high. An alternative to using the
interrupt is to poll the TX DONE bit, looking for a high level.
Set the 16 Collisions Register, BMPR11, to 07H for this test (no
halt, skip-failed packet). Clear status bits by writing 0FF86H to
the Receive and Transmit Status registers. Next, try to transmit
a packet length of 600 or more bits. Up to 16 attempts may be
made automatically, if collisions are indicated. Upon comple-
tion of the transmission attempts, TX DONE goes high, gener-
ating an interrupt if so enabled. When this occurs, read the
Transmit Status register and the TDR register.
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