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參數(shù)資料
| 型號： | MB86964PFV-G |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100 |
| 封裝： | SHRINK, PLASTIC, QFP-100 |
| 文件頁數(shù)： | 34/52頁 |
| 文件大?。?/td> | 373K |
| 代理商： | MB86964PFV-G |
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MB86964
4
Buffer Memory Interface Pins
PIN NO.
SYMBOL
TYPE
DESCRIPTION
91-93,
95-99
BD<7:0>
I/O
BUFFER MEMORY DATA BUS: Data lines between the SRAM buffer
memory and the MB86964.
5-12, 14, 15,
17-21
BA<14:0>
O
BUFFER MEMORY ADDRESS BUS: These lines address up to 32 kbytes of
buffer memory.
2
BCS
O
BUFFER RAM CHIP SELECT: Active low signal that is the chip select for the
buffer memory.
3
BWE
O
BUFFER WRITE ENABLE: Active low write enable signal generated during
buffer memory write cycles.
4
BOE
O
BUFFER OUTPUT ENABLE: Active low output enable signal generated dur-
ing buffer memory read cycles.
Power and Transceiver Interface Pins
PIN NO.
SYMBOL
TYPE
DESCRIPTION
1, 26, 51, 52,
69, 70, 82, 83,
94
VCC
I
POWER SUPPLY: +5 Volts
± 5%, for analog and digital circuits.
13, 16, 24, 31,
38, 46, 57, 63,
67, 68, 73, 86,
100
GND
I
GROUND: Digital and analog ground.
78, 79
80, 81
DOP1, 2
DON1, 2
O
AUI TRANSMIT PAIR: A differential output driver pair for the AUI transceiver
DO circuits; output is Manchester-encoded. DOP1 should be tied to DOP2
and DON1 should be tied to DON2 on the circuit board.
76
77
DIP
DIN
I
AUI RECEIVE PAIR: A differential input driver pair for the AUI transceiver DI
circuits; input is Manchester-encoded.
84
85
CIP
CIN
I
AUI COLLISION PAIR: A differential input driver pair for the AUI transceiver
CI circuits. The input is collision signalling or signal-quality error (SQE).
66, 65
71, 72
TPOPA, B
TPONA, B
O
TWISTED-PAIR OUTPUTS: Differential driver output pairs to the twisted-pair
cable. The output is pre-equalized so that no external filter is required.
74
75
TPIP
TPIN
I
TWISTED-PAIR INPUT: A differential input pair from the twisted-pair cable.
89
LEDC
O
COLLISION LED: Open-drain driver for the collision indicator. Output is
pulled low during collision.
88
LEDL
I/O
LINK LED: Open-drain driver for ”link test pass” LED. Output pulls low during
link test pass. If externally tied low, forces internal circuitry to ”Link Pass”
state.
87
LEDT
O
TRANSMIT LED: Open-drain driver for the transmit indicator. Output is
pulled low during transmit.
64
RBIAS
I
BIAS RESISTOR: Controls the bias of the operating circuit; pulled to ground
with a 12.4k
±1% resistor.
61*
62*
CLKO
CLKI
O
I
CRYSTAL OSCILLATOR: A 20-MHz crystal must be connected between
these pins. (See figure 4.)
*
CLKO: Leave unconnected if an external clock is used
CLKI: Input for an external 20MHz clock source
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