參數(shù)資料
型號(hào)： MB86964PFV-G
元件分類： 微控制器/微處理器
英文描述： 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100
封裝： SHRINK, PLASTIC, QFP-100
文件頁(yè)數(shù)： 21/52頁(yè)
文件大小： 373K
代理商： MB86964PFV-G
MB86964
28
TRANSMIT INTERRUPT ENABLE REGISTER
As shown in Table 11, this register contains the bits that enable
the status bits in DLCR0 to generate interrupts. Only bits 7, 3,
2, and 1 can generate interrupts; the other interrupt enable bits
are not used.
RECEIVE INTERRUPT ENABLE REGISTER
As shown in Table 12, this register contains the bits that enable
the status bits in DLCR1 to generate interrupts. Refer to Table
13 for information on setting up the various control bits to per-
form network monitoring and diagnostic functions.
Table 11. DLCR2 - Transmit Interrupt Enable Register
BIT
SYMBOL
TYPE
DESCRIPTION
7
INT EN
RW0
INTERRUPT ENABLE: When high, enables TX DONE to generate interrupt. Also see
DLCR0<7>.
6
0
N0
RESERVED: Write 0.
5
0
N0
RESERVED: Write 0.
4
0
N0
RESERVED: Write 0.
3
JABBER-
INT EN
RW0
INTERRUPT ENABLE: When high, enables JABBER to generate an interrupt. Also see
DLCR0<3>.
2
COL
INT EN
RW0
INTERRUPT ENABLE: When high, enables COL to generate an interrupt. Also see
DLCR0<2>.
1
16 COL
INT EN
RW0
INTERRUPT ENABLE: When high, enables 16 COL to generate interrupt. Also see
DLCR0<1>.
0
0
N0
RESERVED: Write 0.
Table 12. DLCR3 - Receive Interrupt Enable Register
BIT
SYMBOL
TYPE
DESCRIPTION
7
INT EN
RW0
INTERRUPT ENABLE: When high, enables RX PKT to generate interrupt. Also see
DLCR1<7>.
6
INT EN
RW0
INTERRUPT ENABLE: When high, enables BUS RD ERR to generate interrupt. Also see
DLCR1<6>.
5
INT EN
RW0
INTERRUPT ENABLE: When high, enables DMA EOP to generate interrupt. Also see
DLCR1<5>.
4
INT EN
RW0
INTERRUPT ENABLE: When high, enables RMT 0900H to generate interrupt. Also see
DLCR1<4>.
3
INT EN
RW0
INTERRUPT ENABLE: When high, enables SHORT PKT ERR to generate and interrupt.
Also see DLCR1<3>.
2
INT EN
RW0
INTERRUPT ENABLE: When high, enables ALIGN ERR to generate interrupt. Also see
DLCR1<2>.
1
INT EN
RW0
INTERRUPT ENABLE: When high, enables CRC ERR to generate interrupt. Also see
DLCR1<1>.
0
INT EN
RW0
INTERRUPT ENABLE: When high, enables RX BUF OVERFLO to generate interrupt.
Also see DLCR1<0>.
相關(guān)PDF資料
PDF描述
MB86965 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP16
MB86976PF-G 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP144
MB87033BPF SCSI BUS CONTROLLER, PQFP80
MB8867P 21.33 MHz, PROC SPECIFIC CLOCK GENERATOR, PDIP24
MB88R157A OTHER CLOCK GENERATOR, PDSO8
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MB86965 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:EtherCoupler ETHERNET CONTROLLER WITH 10BASE?T TRANSCEIVER
MB86965B 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:EtherCoupler ETHERNET CONTROLLER WITH 10BASE?T TRANSCEIVER
MB86965BPF-G-BND 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:EtherCoupler ETHERNET CONTROLLER WITH 10BASE?T TRANSCEIVER
MB86967 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:LAN Controller with PC Card, ISA Bus, and General-purpose Bus Interfaces
MB86967PFV 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:LAN Controller with PC Card, ISA Bus, and General-purpose Bus Interfaces
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*