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| 型號： | MB86964PFV-G |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100 |
| 封裝： | SHRINK, PLASTIC, QFP-100 |
| 文件頁數(shù)： | 38/52頁 |
| 文件大?。?/td> | 373K |
| 代理商： | MB86964PFV-G |
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MB86964
43
TIMING DIAGRAMS
All specifications are valid over the Recommended Operating Conditions unless otherwise noted.
Table 34. Read Cycle
t1
t3
t2
t5
t4
t6
t9
t8
t7
t10
SA<3:0>
CS
RD
RDY
SD<15:0>
SYMBOL
PARAMETER DESCRIPTION
MINIMUM
MAXIMUM
UNITS
t1
SA<3:0> valid to RD low; CS low to RD low.
3
ns
t2
RD high to SA<3:0> invalid; RD high to CS high.
3
ns
t3
RD low pulse width.
30
ns
t4
RD low to RDY low.
0
26
ns
t5
RD low to RDY high.
For registers and buffer port when port is ready before the read
cycle begins.
0
7
ns
For port access only, if system attempts to make contiguous sys-
tem read cycles at less than 100 ns intervals, and the network is
busy.
0
175
ns
For bus read error.
0
2.15
s
t6
RD low to RDY low:
ns
For all registers.
0
28
ns
For port access only, if system attempts to make contiguous sys-
tem read cycles at less than 100 ns intervals, and the network is
busy.
0
175
ns
For bus read error.
0
2.15
s
t7
RD high to RDY high.
28
ns
t8
RDY high to SD<15:0> valid.
8
ns
t9
RDY low to SD<15:0> valid.
10
ns
t10
RD high to SD<15:0> invalid.
15
25
ns
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