
MB86964
31
RECEIVE MODE REGISTER
As shown in Table 16, this register contains six bits that control
receiver functions, and one receive buffer status bit.
Status bit RX BUF EMPTY, DLCR5<6>, is necessary to the
software routine which reads receive packets from the buffer. It
tells the host whether there are any packets in the receive buffer
that are complete and ready to read. In a multitasking system,
this indicator would be used in conjunction with an interrupt
when RX PKT asserts, which means a packet has arrived in
memory. The interrupt would be used to start the routine that
reads packets from the buffer.
As this routine begins, the interrupt on RX PKT can be disabled
to prevent unneeded interrupts. After the first packet is read
from the buffer, the RX BUF EMPTY bit would be read to see if
more packets have come in (packets may, at times, arrive in
bursts). If the buffer is not empty, another packet would be read
out, and this procedure repeated until the buffer is empty. After
emptying the buffer, the host clears RX PKT, then reenables in-
terrupts on RX PKT, checks the buffer status one more time
(because a packet can arrive at any time), then exits to do other
tasks. Note that the packet header can reflect acceptance of a
short packet (bytes 3 to 59).
Two of the control bits allow reception of packets with certain
types of errors. The ACPT BAD PKTS bit, when set, causes
the Receiver to retain and store in the buffer packets with CRC,
alignment or short-length errors, provided that there was no in-
dication of collision during reception. Likewise, the ACPT
SHORT PKTS bit, when set, allows the retention of short pack-
ets down to and including only six bytes in length, excluding
Preamble and CRC, provided that there was no indication of
collision during reception and no alignment or CRC error. Un-
der normal operation, packets with less than 60 bytes, the IEEE
802.3 lower limit, would be discarded. These functions are
provided for diagnostic purposes.
Address Filter Mode bits AF1 and AF0 select the destination
addresses for which the MB86964 will accept packets for pro-
cessing. Table 17 provides additional information on the rela-
tionship of the setting of these bits with other control bits and
how they interact in terms of packet reception.
Table 16. DLCR5 - Receive Mode Register
BIT
SYMBOL
TYPE
DESCRIPTION
7
0
N0
RESERVED: Write 0.
6
RX BUF
EMPTY
R1
RECEIVE BUFFER EMPTY: Status bit which indicates that the receive buffer does not
have any complete packets to read.
5
ACPT BAD
PKTS
RW0
ACCEPT BAD PACKETS: When set high, allows packets with CRC and/or alignment errors
or packets that are short to be saved in the receive buffer for analysis. Otherwise such
packets would be discarded automatically by the receiver and removed from the buffer.
4
RX SHORT
ADDR
RW0
RECEIVE SHORT ADDRESS: When set high, instead of customary 48-bit NODE ID ad-
dress filter, only first 40 bits of NODE ID are compared.
3
ACCPT
SHORT
PKTS
RW0
ACCEPT SHORT PACKETS: When set high, allows short packets (with less than 60 bytes,
excluding Preamble and CRC, i.e., below IEEE minimum length) to be saved in the receive
buffer. Otherwise such packets would be discarded automatically by the receiver and re-
moved from the buffer.
2
RMT
CNTRL EN
RW0
REMOTE CONTROL ENABLE: When set high, enables receipt of Remote Control Pack-
ets. See DLCR1<4>.
1
0
AF1
AF0
RW1
RW0
ADDRESS FILTER MODE: These two bits control the address filtering on incoming pack-
ets. Note that self reception of broadcast and multicast packets is prohibited except in ac-
cept all packets and loopback modes. When LBC is low (loopback mode), broadcast pack-
ets can be self-received, except in reject all packets mode.
AF1
AF0
ACCEPTABLE ADDRESS DESCRIPTIONS
0
1
— NODE ID
— Broadcast
— Multicast and 2nd-24th bits of NODE ID.
1
0
— NODE ID
— Broadcast,
— Multicast and Hash Table.
0
0
— Reject all packets.
1
1
— Accept all packets.