參數(shù)資料
型號: MB86964PFV-G
元件分類: 微控制器/微處理器
英文描述: 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100
封裝: SHRINK, PLASTIC, QFP-100
文件頁數(shù): 41/52頁
文件大?。?/td> 373K
代理商: MB86964PFV-G
MB86964
46
Table 37. Burst DMA Timing
t1
t2
DREQ
DMACK
RD or WR
RDY
t1
SYMBOL
PARAMETER DESCRIPTION
MINIMUM
MAXIMUM
UNITS
t1
RD or WR low to DREQ low
32
ns
t2
RD or WR high to DMACK high
3
ns
All of the RD or WR asserted pulse must fall inside of the DMACK asserted pulse. The DMA cycle uses DMACK as the chip select. DMACK
overrides SA<3:0>, forcing selection of the buffer memory port. DREQ goes low during the next-to-last transfer of the burst if DLCR4<2> = 1, and
can be extended to the last transfer cycle by setting DLCR4<2> = 0.
DREQ
DMACK
RD or WR
RDY
BURST INTERRUPTED
Burst can be interrupted by negating DMACK. Burst will resume when DMACK is reasserted.
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