參數(shù)資料
型號(hào)： MB86964PFV-G
元件分類(lèi)： 微控制器/微處理器
英文描述： 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100
封裝： SHRINK, PLASTIC, QFP-100
文件頁(yè)數(shù)： 3/52頁(yè)
文件大?。?/td> 373K
代理商： MB86964PFV-G
MB86964
11
4. The transmitter obtains data for transmission from the
transmit buffer.
5. Any combination of the above can occur concurrently.
HOST CPU
READ
OR
WRITE
TRANSMIT
NETWORK
MB86964
BUFFER
CONTROLLER
DEDICATED
BUFFER MEMORY
INTERLEAVED
DATA
RECEIVE
Figure 6. Simultaneous Access to Buffer Memory
Transmit Buffer
The section of the memory used by the transmitter can be con-
figured by programming the Transmitter Buffer Size control
bits, DLCR6<3:2>. Configurations include a single buffer 2
kilobytes long, or a pair of banks, each either 2, 4 or 8 kilobytes
long, as illustrated in Figure 7. Within each buffer or bank, one
or more packets can be written by the system until the available
space is too small for another packet. When a single transmit
buffer is used, the system and the transmitter time-share the use
of the buffer. When two buffers are used, the system can load
packets into one of the buffers while the contents of the other
are being transmitted. Using dual buffers and loading multiple
packets for ’packet chaining’ gives the highest rate of transmis-
sion.
At reset, internal pointers are initialized to point to the begin-
ning of one of the transmit buffers. Each time the host writes
data to the buffer via the Buffer Memory Port Register, an inter-
nal pointer is advanced to the next memory location within the
transmit buffer. Once a data byte/word is written, it cannot be
read and the internal pointer cannot be reversed.
When the host completes loading the transmit buffer, it writes
the number of packets it has loaded into TX PKT CNT,
BMPR10<6:0> and sets the transmit start bit, BMPR10<7>.
When this occurs, the MB86964 will switch banks and will
start transmitting at the earliest opportunity. Another automati-
cally-managed pointer, the transmit read pointer, sequences
through the bank being transmitted to read the packet data into
the transmitter through its FIFO. If a collision occurs, the pack-
et will be automatically retransmitted after a pseudo-random
waiting interval called the backoff interval. If there are multi-
ple packets in the buffer, the MB86964 will continue down the
list until all are transmitted. Upon reaching the end of the list or
chain of packets, the transmitter will stop, update its status bits
and, if enabled, generate an interrupt. The details of this opera-
tion are described in the section on packet transmission.
Transmit Packet Header
As shown in Figure 8, each packet within one transmit bank is
separated by a non-transmitted, two-byte header containing an
11-bit value which specifies the length of the associated packet
in bytes. The length specification includes only what is stored
in the buffer (shown in the figure as ’DATA’), which are the
Destination ID, Source ID, Length, and Data fields of the pack-
et. It does not include the Preamble and CRC fields which are
generated by the MB86964 as it transmits the packet, and there-
fore are not stored in the buffer.
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