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| 型號： | MB86964PFV-G |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100 |
| 封裝： | SHRINK, PLASTIC, QFP-100 |
| 文件頁數(shù)： | 30/52頁 |
| 文件大?。?/td> | 373K |
| 代理商： | MB86964PFV-G |
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MB86964
36
Table 22. Collision Action Codes Written to BMPR11
ACTION CODE
ACTIONS
02H or 03H
MODE SETUP: Halt after 16 collisions.
02H
COMMAND: Resume transmitting, repeat current packet. For use following a halt. Terminates the halt.
Instructs transmitter to resume transmitting, repeating the current packet. The collision counter is reset, allow-
ing up to 16 additional attempts to be made. Transmitter will again halt after 16 collisions.
03H
COMMAND:
Resume transmitting, skip failed packet. For use following a halt. Terminates the halt.
Instructs transmitter to skip the failed packet and resume transmitting with the next packet in the buffer. The
collision counter is reset, allowing up to 16 additional attempts to be made. If there is no next packet, the
transmitter deactivates, setting TX DONE bit, DLCR0<7>, as it does so. The transmitter halts after 16 colli-
sions.
06H
MODE SETUP: Continue automatically after 16 collisions, repeat failed packet. Note that if the network me-
dium disconnects, transmission attempts usually result in false collision detection. Under this condition, this
mode causes transmitter to continue attempting transmission of the same packet indefinitely. Interrupt or peri-
odic polling of the status bits could detect this condition.
07H
MODE SETUP: Continue automatically after 16 collisions, skip failed packet. Note that this mode results in
failure to transmit some packets, because it skips a packet that has had 16 consecutive collisions. While this
condition is rare on a healthy network, it does occur occasionally.
DMA ENABLE REGISTER
Table 23 describes the DMA Enable register, BMPR12, a regis-
ter that enables or clears receive read DMA or transmit write
DMA.
Table 23. BMPR12 - DMA Enable Register
BIT
SYMBOL
TYPE
DESCRIPTION
7 - 2
0
N0
RESERVED: Write 0.
1
RX DMA
EN
RW0
RECEIVE DMA ENABLE When set to 0, disables DMA read. When set to 1, enables DMA
read.
0
TX DMA
EN
RW0
TRANSMIT DMA ENABLE: When set to 0, disables DMA write. When set to 1, enables
DMA write.
RX DMA EN
TX DMA EN
ACTIONS
0
0
Clear or terminate DMA activity, DMA EOP status bit and
associated interrupt, if any. Normally used as response to
end of process (DMA EOP) interrupt.
0
1
Enable transmit write DMA.
1
0
Enable receive read DMA.
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