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參數(shù)資料
| 型號(hào)： | MB86964PFV-G |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100 |
| 封裝： | SHRINK, PLASTIC, QFP-100 |
| 文件頁數(shù)： | 50/52頁 |
| 文件大?。?/td> | 373K |
| 代理商： | MB86964PFV-G |
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MB86964
7
LOCAL BUFFER CONFIGURATIONS
The MB86964 is designed to operate with local buffer which
holds packets received from the host processor prior to trans-
mission and assembles packets received from the network be-
fore they are delivered to the host processor. The buffer is im-
plemented by using a single byte-wide SRAM whose size is
selected via DLCR6<1> as 8 kbytes (DLCR6<1> = 0) or 32
kbytes DLCR6<1> = 1).
See Buffer Access section for information on how the host ac-
cesses the buffer memory.
POWER DOWN MODE
When the MB86964 is not in use, the power down feature re-
duces power consumption by shutting off all internal clocks.
This feature is invoked by first setting the DLC EN bit,
DLCR6<7>, high, thus disabling the receiver and transmitter,
and then by setting the PWRDN bit, DLCR7<5>, low. The
power down mode terminates by setting the PWRDN bit high
(writing a one to DLCR7<5>) or by performing a hardware re-
set. Contents of all registers are maintained during power
down and remain unchanged, except if power down mode is
terminated by a hardware reset.
SYSTEM INTERFACE
General
The system interface provides the interface logic necessary to
connect to an x86, RISC or 680X0-type microprocessor bus.
The interface supports 8- and 16-bit bus widths and byte or
word transfers. The data path width between the host and the
MB86964 is controlled via DLCR6<5>. When this bit is a ’1’,
the system bus interface is programmed to operate in 8-bit
mode; when it is a ’0’, 16-bit mode is selected. The inverse of
the programmed value appears at pin 43, SW. The interface de-
faults to 8-bit mode after a hardware reset, thus initial access to
the chip must utilize 8-bit data transfers. The data is supplied
MSB or LSB first (big or little endian), according to the setting
of the M..L/L..M bit, DLCR7<0>. The setting of this bit only
affects data transfers between the host and the buffer memory;
data transfers between the host and the other MB86964 regis-
ters are not affected by the setting of the M..L/L..M bit. The
MB86964 supports I/O-mapped operation and burst or single-
transfer DMA modes. An interrupt request output, pin 59, in-
forms the CPU of transmit and receive status conditions requir-
ing host processing.
Byte-Order Control
Byte-order control provided by Most..Least/Least..Most bit,
DLCR7<0>, provides compatibility with various higher-level
protocols, such as TCP/IP and XNS. These protocols may have
a different order for transmission of the bytes within a word.
When M..L/L..M is low, the least-significant byte of the word
transmits first, followed by the most-significant. When M..L/
L..M is set high, the byte order reverses. This feature applies
only when the system bus operates in 16-bit (word) mode.
The byte-order control works by reversing, or not reversing,
the bytes of all words as they pass between the buffer memory
and the system bus. Thus all data stored in the transmit buffer
or retrieved from the receive buffer is affected, including non-
transmitted headers.
This control bit does not affect the
MB86964 registers other than the Buffer Memory Port regis-
ters, BMPR8 and BMPR9. When using this feature, ensure the
reversal of header information as well as packet data in the soft-
ware driver code. See Table 1 for examples of using least..most
and most..least byte ordering.
Register Access
The MB86964 includes four sets of user-accessible registers,
all of which are accessible as bytes or words. Each register set
contains eight registers.
Direct access is available to two sets of registers in the device’s
register set at a time, via register addresses 00H through 0FH.
The Data Link Control Registers set (DLCR0 - DLCR7) is al-
ways accessible via addresses 00H to 07H. Access to one of the
remaining three sets is accomplished by programming the reg-
ister bank select bits, DLCR7<3:2>. This selects the register
set accessible via addresses 08H to 0FH. The bank-switched
registers are the Node ID set , DLCR7 - DLCR15, (for setting
the Ethernet Address and performing TDR diagnostics), the
Hash Table set, HT8 - HT15, (for setting up multicast address
filtering) and the Buffer Memory Port set, BMPR7 - BMPR15.
During operation (excluding initialization or diagnostics), the
Buffer Memory Port set should normally be selected.
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