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參數資料
| 型號： | MB86964PFV-G |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100 |
| 封裝： | SHRINK, PLASTIC, QFP-100 |
| 文件頁數： | 31/52頁 |
| 文件大?。?/td> | 373K |
| 代理商： | MB86964PFV-G |
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MB86964
37
DMA BURST AND TRANSCEIVER
MODE REGISTER
Table 24 describes the DMA Burst and Transceiver Mode reg-
ister, BMPR13, which selects the burst length for DMA opera-
tion and programs the 10BASE-T transceiver modes. Burst
length is defined as the number of data transfers occurring dur-
ing one acquisition of the system bus. After the programmed
number of transfers, the bus is released and a new bus arbitra-
tion cycle will be started. Each transfer is one word or one byte,
depending on System Byte/System Word mode selected via
DLCR6<5>.
Table 24. BMPR13 - DMA Burst and Transceiver Mode Register
BIT
SYMBOL
TYPE
DESCRIPTION
7
1
N0
Reserved.
6
LOWER
SQLCH
THRESH
WR0
LOWER SQUELCH THRESHOLD: When set to 1, reduces twisted-pair squelch threshold
by 4.5 dB. When set to 0, twisted-pair squelch threshold is normal.
5
LINK TEST
EN
WR0
LINK TEST ENABLE: When set to 1, disables transmit and receive link integrity test func-
tions. When set to 0, enables link integrity test.
4
AUI / TP
WR0
AUI /TP PORT SELECT: When AUTO PORT SELECT bit, BMPR13<3>, is set to 1, this bit
selects the active network port. When set to 1, the AUI port is selected. When set to 0, the
10BASE-T twisted-pair port is selected.
3
AUTO
PORT SEL
WR0
AUTOMATIC PORT SELECTION: When set to 0, automatic port selection mode is in effect.
Defaults to the AUI port if twisted-pair link integrity fails. When set to 1, allows port selection
via AUI/TP bit, BMPR13<4>.
2
STP / UTP
WR0
STP / UTP SELECT: When set to 1, selects 150
termination for shielded twisted pair.
When set to 0, selects 100
termination for unshielded twisted pair.
1
0
BURST 1
BURST 0
WR0
BURST CONTROL: Selects the burst length for DMA operation.
BURST 1
BURST 0
BURST LENGTH (TRANSFERS)
0
0
1
0
1
4
1
0
8
1
1
12
FILTER SELF RECEIVE REGISTER
Table 25 describes the Filter Self Receive Register, BMPR14.
[Also refer to Table 17 for more information about the Filter
Self Receive function.]
Writing a ‘1’ to bit 2 of this register commands the buffer con-
troller to skip the balance of the current receive packet in
memory. The bit can then be read to determine that completion
of the skip process is complete (within 300 ns). If there is
another packet, the bit returns to 0 when the chip is ready to read
the next packet or, if there is not another packet, stop reading.
Do not use this feature before reading at least four times from
the beginning of the packet, nor if there are eight or fewer bytes
left of the packet in the buffer; doing so may corrupt the receive
buffer pointers.
As shown in the table, this register also provides control for en-
abling interrupts based on the setting of status bits in BMPR15,
the Transceiver Status Register.
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