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參數(shù)資料
| 型號： | MB86964PFV-G |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100 |
| 封裝： | SHRINK, PLASTIC, QFP-100 |
| 文件頁數(shù)： | 19/52頁 |
| 文件大?。?/td> | 373K |
| 代理商： | MB86964PFV-G |
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MB86964
26
TRANSMIT STATUS REGISTER
As shown in Table 9, this register provides transmit status for
the host processor. The system can enable interrupts based on
setting (active high) of bits 7, 3, 2, or 1 of this register by setting
the corresponding interrupt enable bits in the Transmit Inter-
rupt Enable register, DLCR4.
Bits 7, 3, 2, and 1 of this register, which can generate interrupts,
are cleared by writing a ‘1’ to the bit. Writing ‘0’ to these bits
has no effect. Only the MB86964 control logic can set these
bits to high. Clearing the bit that causes an interrupt clears the
bit and the interrupt. Because two or more status conditions
may occur simultaneously, the interrupt routine must read and
act on all status conditions that are set.
One method to clear interrupts is to read the contents of the sta-
tus register, then write the same value back to the register, thus
clearing all bits that were set. Another technique is to clear each
status bit separately, by writing its mask (interrupt enable) to
the register. This might be done as the corresponding interrupt
service is performed. Note that wholesale clearing of all status
bits by writing FFH to the register is not recommended, be-
cause this action may clear a just-set status that has not yet been
read by the system. Note also that the transmitter must be idle
and TX DONE, DLCR0<7>, must be cleared by writing 1 to it
before starting the transmitter by writing 1 to TXSTART,
BMPR10<7>.
Table 9. DLCR0 - Transmit Status Register
BIT
SYMBOL
TYPE
DESCRIPTION
7
TX DONE
RC0
TRANSMIT DONE: This bit is set high when all packets in the active transmit buffer have
been successfully transmitted to the LAN media, or skipped due to excessive collisions.
Can generate interrupt if enabled by DLCR2<7>.
6
NET BSY
R
NET BUSY: This is a real-time image of the carrier sense signal of the receiver.
5
TX PKT
RCD
R0
TRANSMIT PACKET RECEIVED: Indicates that a good packet was received shortly after
transmission was completed. This is used to indicate self-reception of the packet. This bit is
cleared as each transmission begins.
4
CR LOST
R0
CARRIER LOST: This bit is set if the receive carrier sense input is negated during a packet
transmission. This can be caused by a collision or a shorted LAN medium. It is automati-
cally cleared as each transmission begins.
3
JABBER
RC0
JABBER: When active high, indicates excessive transmit length is detected by the JAB-
BER timer. Can generate interrupt if enabled by DLCR2<3>.
2
COL
RC0
COLLISION: This bit will assert during transmission of a data packet if a collision occurs on
the network. The buffer controller will automatically retransmit the current packet after colli-
sions up to 16 times. The user may read the number of consecutive collisions in collision
counter, DLCR4<7:4>. Can generate interrupt if enabled by DLCR2<2>.
1
16 COL
RC0
16 COLLISIONS: This bit is set after the sixteenth unsuccessful transmission of the same
packet. Can generate interrupt if enabled by DLCR2<1>.
0
0
R0
RESERVED: Write 0.
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