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參數(shù)資料
| 型號(hào)： | MB86964PFV-G |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100 |
| 封裝： | SHRINK, PLASTIC, QFP-100 |
| 文件頁數(shù)： | 51/52頁 |
| 文件大小： | 373K |
| 代理商： | MB86964PFV-G |
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MB86964
8
Table 1. Byte Ordering
DATA <15:8>
DATA <7:0>
FOR TRANSMIT PACKET
LEAST. . . . MOST
Transmit Length, high byte
Transmit Length, low byte
Destination Address, 2nd byte
Destination Address, 1st byte
Source Address, 2nd byte
Source Address, 1st byte
Length Field, low byte*
Length Field, high byte*
Data Field, 2nd byte
Data Field, 1st byte
MOST . . . . LEAST
Transmit Length, low byte*
Transmit Length, high byte*
Destination Addr, 1st byte
Destination Addr, 2nd byte
Source Addr, 1st byte
Source Addr, 2nd byte
Length Field, high byte
Length Field, low byte
Data Field, 1st byte
Data Field, 2nd byte
FOR RECEIVE PACKET
LEAST. . . . MOST
Unused, reserved
Receive Packet Status
Receive Length, high byte
Receive Length, low byte
Destination Address, 2nd byte
Destination Address, 1st byte
Source Address, 2nd byte
Source Address, 1st byte
Length Field, low byte*
Length Field, high byte*
Data Field, 2nd byte
Data Field, 1st byte
MOST . . . . LEAST
Receive Packet Status
Unused; reserved
Receive Length, low byte*
Receive Length, high byte*
Destination Addr, 1st byte
Destination Addr, 2nd byte
Source Addr, 1st byte
Source Addr, 2nd byte
Length Field, high byte
Length Field, low byte
Data Field, 1st byte
Data Field, 2nd byte
Items shown with an astertisk are in numerically reversed byte order
Buffer Access
The Buffer Memory Port register pair BMPR8 and BMPR9
provide 8- or 16-bit data access to the receive and transmit buff-
ers through on-chip FIFOs. To eliminate the need for compli-
cated directional control, FIFOs are dedicated to each direction
of data transfer. Writing to the transmit buffer can be inter-
leaved with reading from the receive buffer, with the MB86964
automatically maintaining buffer memory pointers, thus re-
lieving the host of that task. The Buffer Memory port register
pair is at address 08H when DLCR7<3:2> are programmed to
’10’ to select the Buffer Memory Port register set. When using
DMA, the buffer memory port is automatically selected when
the DMA Acknowledge input, DMACK, is asserted. The host
accesses are byte-wide when the system is configured for byte-
wide operation and word-wide when the system interface is
configured for word-wide operation. In the latter mode, byte-
wide access to the buffer memory port is not supported.
Data can transfer from the host memory to the transmit buffer,
or from the receive buffer to host memory by using string
moves, single-transfer programmed I/O moves, or DMA. Se-
lect the method that yields the highest system-level efficiency.
A rapid transfer process results in best performance. Slow
transfer can result in poor throughput and performance, and
cause the receive buffer to overflow and lose packets.
DMA Operation
The MB86964 supports single-cycle and burst DMA operation
for data transfers between the host and the packet buffer. Hand-
shaking between the MB86964 and the external DMA control-
ler is accomplished by the DREQ and DMACK signals. The
end of process input, pin 60, when asserted by the system DMA
controller during a transfer cycle, terminates DMA activity
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