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參數(shù)資料
| 型號： | MB86964PFV-G |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100 |
| 封裝： | SHRINK, PLASTIC, QFP-100 |
| 文件頁數(shù)： | 14/52頁 |
| 文件大?。?/td> | 373K |
| 代理商： | MB86964PFV-G |
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MB86964
21
CONTROL AND STATUS REGISTERS
The control and status registers on the MB86964 are accessed
through register addresses 00H through 0FH, and register
bank-switching bits RBS1 and RBS0, DLCR7<3:2>. Table 3
summarizes the internal registers and their addresses. In 16-bit
mode, even-numbered direct addresses select the registers. For
example, address 00H accesses the Transmit and Receive Sta-
tus registers simultaneously. Transmit Status would be on the
low byte and Receive Status on the high byte. Appropriate
byte-access processor instructions can access high and low by-
tes separately.
Tables 4 - 8 summarize the control and status bits within each
addressable register, as well as the bits in the receive and trans-
mit packet headers. The registers are descibed more fully in the
tables that follow.
The abbreviation that appears in the TYPE column of the fol-
lowing tables are described in the legend below.
TYPE CODE
DESCRIPTION
R
Readable
W
Writable
N
Not used, reserved; write 0 when
written.
C
Writing a 1 clears status bit (and in-
terrupt if enabled). Writing a 0 has
no effect.
0/1
Initial state after hardware reset.
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