參數(shù)資料
型號(hào)： MB86964PFV-G
元件分類(lèi)： 微控制器/微處理器
英文描述： 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100
封裝： SHRINK, PLASTIC, QFP-100
文件頁(yè)數(shù)： 52/52頁(yè)
文件大?。?/td> 373K
代理商： MB86964PFV-G
MB86964
9
after completion of the current cycle. If a DMA interrupt
(DLCR3<5>) is enabled, the MB86964 generates an interrupt
after completion of DMA activity.
Usually only one DMA operation will be run at a time, although
the MB86964 could run two interleaving operations, one read-
ing and one writing. There is only one DMA EOP bit, and only
one DREQ pin and one DMACK pin, so most hosts could not
support more than one DMA operation at a time.
DMA Write (Transmit)
Setting the TX DMA Enable bit, BMPR12<0>, enables DMA
transfer of data packets from the host memory to the MB86964
transmit buffer. The DMA burst control bits, BMPR13<1:0>,
set the maximum number of data transfer cycles (bytes or
words) in a single bus acquisition to be 1, 4, 8, or 12. The
MB86964, when ready to accept data from the host, sets the
DMA request output, DREQ, and the host responds by assert-
ing DMA acknowledge, DMACK, followed by Write Strobe,
WR, and placing data on the data bus. The MB86964 asserts
the RDY(RDY) output when ready to complete the current
data-transfer cycle. (The assertive states of the RDY(RDY)
output and the EOP(EOP) input are independently program-
mable.) The MB86964 accepts the data byte/word into its bus
write FIFO and later moves it into buffer memory. At the close
of a transfer cycle, the host negates WR. In burst mode and de-
pending on the value of the DREQ EXTND bit, DLCR4<2>,
the MB86964 negates DREQ at the next-to-last or last transfer
cycle of the burst. The host DMA then completes the last one or
two transfer cycles and negates DACK to terminate the burst.
To start another burst, the MB86964 reasserts DREQ.
The DMA controller asserts the end of process input,
EOP(EOP), concurrent with the last required data-transfer
cycle to indicate completion of the entire transfer process. This
action sets the DMA EOP status bit, DLCR1<5>, and discon-
tinues further data requests from the MB86964. The MB86964
will also generate an interrupt if the DMA EOP interrupt enable
bit, DLCR3<5>, is high. The host can use this interrupt to be-
gin action to close the process. The host should reset the
MB86964 DMA logic and clear the interrupt by writing 00H to
BMPR12.
Note: DMA EOP, DLCR1<5> must be cleared to close the
transmit DMA process before attempting another DMA pro-
cess. This is accomplished by writing 00H to BMPR12. When
this is done, the DMA EOP bit will clear automatically, clear-
ing the EOP status and interrupt, (if enabled) so it is not neces-
sary to clear the interrupt separately.
After finishing the loading of packets into the buffer, the host
initiates packet transmission. This is done by loading the num-
ber of packets to be transmitted into the Transmit Start Register,
BMPR10<6:0>, and asserting the Transmit Start bit, TX
START, of the same register, BMPR10<7>.
DMA Read (Receive)
The MB86964 indicates that it has received packets and stored
them in the packet buffer with status bits or interrupts. Before
attempting to transfer a packet from the buffer, the host proces-
sor should read the RX BUF EMPTY bit, DLCR5<6>. If this
bit is 0, there are one or more packets ready for transfer in the
receive buffer. After reading each packet, the host will check
this bit again to see if there are more.
Prior to beginning the transfer of a packet from the receive
buffer to host memory via DMA, the host must first read the
four-byte receive packet header from the buffer to obtain the
packet status and the length of the packet in bytes. Calculating
from the packet length the number of DMA cycles needed to
read the packet, the host will load that number into the cycle
counter of the host DMA controller. Next, RX DMA EN,
BMPR12<1>, is set to high to enable DMA read operation to
transfer the packet to host memory. The DMA burst control
bits, BMPR13<1:0>, set the maximum number of data transfer
cycles (bytes or words) in a single bus acquisition to be 1, 4, 8,
or 12. When it is ready to begin, the MB86964 asserts its DMA
Request output, DREQ. The host responds by asserting DMA
Acknowledge, DMACK, followed by the Read Strobe, RD.
The MB86964 will assert its RDY(RDY) output when it has
placed the byte/word on the data bus and is ready to complete
the data transfer cycle. The system memory will accept the
data, then the host negates RD. The MB86964 shifts the data
down in its bus read FIFO, then moves its internal read pointer
to point to the next byte/word in the buffer, moving it into the
FIFO.
In burst mode and depending on the value of the DREQ
EXTND bit, DLCR4<2>, the MB86964 negates DREQ at the
next-to-last or last transfer cycle of the burst. The host DMA
then completes the last one or two transfer cycles and negates
DMACK to terminate the burst.
The MB86964 reasserts
DREQ to repeat the process if it can transfer more data after the
host negates DMACK. The DMA controller asserts the end of
process input, EOP(EOP) concurrent with the last byte/word
data transfer to indicate completion of the entire process. The
MB86964 then stops requesting more DMA cycles.
When EOP(EOP) is asserted by the host DMA controller, the
DMA EOP bit, DLCR1<5>, will be set high, and an interrupt
will also be generated, provided it is enabled by a high in the
associated interrupt enable bit, DLCR3<5>. This interrupt can
be used by the host to initiate the final actions to close the DMA
process. The interrupt is cleared and the DMA is disabled and
reset by writing 00H to the DMA Enable Register, BMPR12.
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