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參數(shù)資料
| 型號： | MB86964PFV-G |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100 |
| 封裝： | SHRINK, PLASTIC, QFP-100 |
| 文件頁數(shù)： | 28/52頁 |
| 文件大?。?/td> | 373K |
| 代理商： | MB86964PFV-G |
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MB86964
34
Table 19. DLCR7 - Configuration Register 1
BIT
SYMBOL
TYPE
DESCRIPTION
7
6
CID 1
CID 0
R0
R1
CHIP IDENTIFICATION: A code which identifies this chip as the MB86964.
5
PWRDN
RW1
POWER DOWN: When set high, enables power to the chip for all functions; when set low,
places chip in power down mode for power conservation.
4
RDYPOL
R 0/1
READY PIN POLARITY: Reflects the state of RDYPOL mode setting at pin 36.
3
2
RBS 1
RBS 0
RW0
REGISTER BANK SELECT: Provides the indirect address for selecting one of three sets of
registers to access when the physical register address is 08H - 0FH. The lower eight regis-
ters are not bank-selectable.
RBS1
RBS0
REGISTERS
0
0
DLCR0
DLCR7, DLCR8 DLCR15
0
1
DLCR0
DLCR7, HT8 HT15
1
0
DLCR0
DLCR7, BMPR 8 BMPR15
1
1
Reserved.
1
EOPPOL
RW0
EOP PIN SIGNAL POLARITY: When high, the EOP input pin is active-high; when low,
EOP is active-low.
0
M..L / L..M
RW0
BYTE ORDER CONTROL: Selects byte lane ordering for packet data in the buffer (applies
only in system word mode). When this bit is high (M..L mode), the first and all odd-num-
bered bytes of a packet and its header appear on the high byte of the system bus. When
low, the first and all odd-numbered bytes of a packet appear on the low byte. Note that
header bytes are also swapped. This bit does not effect data transfers to/from the internal
registers, except the buffer port registers BMPR8 and BMPR9.
NODE ID REGISTERS
The Node ID Registers are accessed in register bank ”00” at
register addresses 08H - 0DH. During node initialization, the
unique Ethernet address assigned to the node is loaded into
these registers. The first register at 08H corresponds to the first
byte to be received as a packet arrives from the network. If the
MB86964 is configured via Address Filter bits DLCR5<1:0>
to match node ID, the destination address field of an incoming
packet is compared with the contents of these registers. The
packet is accepted if it passes the error filter and there is a
match.
The Node ID registers are readable and writable registers, and
should not be accessed while the Receiver is enabled. To avoid
interaction with the Receiver, it is recommended that the Node
ID registers be written and read only during initialization, be-
fore enabling the receiver, i.e., before writing 0 to DLC EN.
The address contained in the Node ID registers is used only for
receive (destination) address filtering, not for the source ad-
dress of outgoing packets. The system provides outgoing pack-
et addresses as part of the packet data. Within each byte, bits are
transmitted and received on the network in a least-significant-
bit-first order.
TIME DOMAIN REFLECTOMETRY (TDR) COUNTER
The TDR Counter approximately indicates the location of a
fault on the network, if one exists. The TDR Count comes from
DLCR14 (the least-significant byte) and DLCR15 (the most-
significant byte). The top two bits, DLCR15<7:6>, are always
0.
Refer to the transmitter section for additional information on
the TDR counter, performing a TDR test and interpreting the
results.
BUFFER MEMORY PORT REGISTER
Buffer Memory Port register BMPR8 provides the host with
access to buffer memory. Register Bank Select bits RBS1 and
RBS0, DLCR7<3:2>, are set to 1 and 0, respectively, to access
the buffer memory port and the other control and status regis-
ters described in this section.
Writing a byte/word to BMPR8 transfers that data to the cur-
rently addressed location in the transmit buffer, and increments
the transmit buffer pointer to point to the next byte/word.
Reading a byte/word from this port transfers the contents of the
currently addressed location in the receive buffer to the host,
and increments the receive buffer pointer to point to the next
byte/word.
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相關(guān)代理商/技術(shù)參數(shù) |
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| MB86965 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:EtherCoupler ETHERNET CONTROLLER WITH 10BASE?T TRANSCEIVER |
| MB86965B | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:EtherCoupler ETHERNET CONTROLLER WITH 10BASE?T TRANSCEIVER |
| MB86965BPF-G-BND | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:EtherCoupler ETHERNET CONTROLLER WITH 10BASE?T TRANSCEIVER |
| MB86967 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:LAN Controller with PC Card, ISA Bus, and General-purpose Bus Interfaces |
| MB86967PFV | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:LAN Controller with PC Card, ISA Bus, and General-purpose Bus Interfaces |
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