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參數(shù)資料
| 型號： | MB86964PFV-G |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100 |
| 封裝： | SHRINK, PLASTIC, QFP-100 |
| 文件頁數(shù)： | 4/52頁 |
| 文件大小： | 373K |
| 代理商： | MB86964PFV-G |
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MB86964
12
BANK0
2KILOBYTES
TRANSMIT
SECTION
RECEIVE
SECTION
6KILOBYTES
BANK0
2KILOBYTES
TRANSMIT
SECTION
RECEIVE
SECTION
4KILOBYTES
2KILOBYTES
BANK1
BANK0
2KILOBYTES
TRANSMIT
SECTION
RECEIVE
SECTION
30KILOBYTES
BANK0
2KILOBYTES
TRANSMIT
SECTION
RECEIVE
SECTION
28KILOBYTES
2KILOBYTES
BANK1
BANK0
4KILOBYTES
TRANSMIT
SECTION
RECEIVE
SECTION
24KILOBYTES
BANK0
8KILOBYTES
TRANSMIT
SECTION
RECEIVE
SECTION
16KILOBYTES
8KILOBYTES
BANK1
4KILOBYTES
BANK1
Using 32 kx8 SRAM
Using 8kx8 SRAM
Figure 7. Transmit Buffer Configurations
Receive Buffer
Once initialized and enabled, the receiver will automatically
load any error-free incoming packets which pass the address
filter into the receive buffer through an on-chip FIFO. An inter-
rupt can be provided to alert the host processor that a packet is
available in the buffer. The host processor can read out re-
ceived packets as they become available. Continuous recep-
tion can continue as long as the receive buffer does not become
full. If the host processor reads the receive packets from the
buffer promptly, the buffer will not fill up. If overflow does oc-
cur, the receiver will stop and an interrupt will be generated to
indicate the problem. If this occurs, the buffer should be emp-
tied so that reception can resume. As soon as space becomes
available in the receive buffer, the receiver will automatically
resume reception.
The receive buffer size can vary between a maximum of 30 ki-
lobytes when 2 kilobytes are allocated for the transmit section
and a 32 kilobyte SRAM is used, to a minimum of 4 kilobytes if
4 kilobytes are allocated for the transmit section and an 8 kilo-
byte SRAM is used. The receive section dynamically allocates
space for each individual incoming data packet, aligning each
at an eight-byte ’page’ boundary. Each received packet is pre-
ceded by a four byte header which provides packet status and
the length of that data packet. The data packets are linked or
chained by internal pointers which use the length value in the
packet header to calculate the starting address of the next pack-
et.
This buffer format is shown in Figure 9.
Since the
MB86964 controls its dedicated buffer memory, FIFO size and
depth are unimportant in this architecture, and need not be con-
sidered in system timing considerations.
A status bit in one of the MB86964’s internal registers informs
the host when one or more packets are resident in the receive
buffer and available to be read. The host retrieves these packets
from the buffer memory by successive reads of BMPR8. Once
a data byte/word is read from the buffer memory, internal point-
ers are advanced to the next byte/word. As data is thus read by
the system, that memory becomes available for reception of
new packets. The MB86964 automatically rejects an incom-
ing packet if there is not enough buffer space to fully receive
that packet. Therefore, there is no chance for packets already
received to be ’overrun’ by incoming packets.
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