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參數(shù)資料
| 型號： | MB86964PFV-G |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100 |
| 封裝： | SHRINK, PLASTIC, QFP-100 |
| 文件頁數(shù)： | 2/52頁 |
| 文件大?。?/td> | 373K |
| 代理商： | MB86964PFV-G |
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MB86964
10
Note: Clearing RX DMA EN must be done to close the receive
DMA process before attempting another DMA process. This is
accomplished by writing 00H to BMPR12. When this is done,
the DMA EOP bit will clear automatically, clearing the EOP
status and interrupt, so it is not necessary to clear the interrupt
separately.
After completion of the DMA process, RX DMA EN must be
reasserted when the host wants to begin reading another packet
from the receive buffer by using DMA.
BUFFER CONTROLLER
TRANSMIT BUFFERS
RECEIVED PACKET n+3
(LAST PART)
CURRENTLY AVAILABLE
FREE BUFFER AREA
RECEIVED PACKET n
RECEIVED PACKET n + 1
RECEIVED PACKET n + 2
RECEIVED PACKET n + 3
(FIRST PART)
RECEIVE BUFFER RING
(30 KILOBYTES MAX)
ONE OR TWO
TRANSMIT BUFFER
Figure 5. Buffer Memory Organization
General
The MB86964 uses a dedicated buffer memory, organized as
shown in Figure 5, for intermediate storage of packets to be
transmitted, and of packets received from the network. The
MB86964 can operate with 8 or 32 kilobytes of total buffer
memory, including both transmit and receive spaces. Memory
partitioning into transmit and receive sections is controlled by
the system software. The total size of the transmit buffer space
can be up to 16 kilobytes. The buffer memory not used for the
transmitter is used for the receiver, and is automatically config-
ured as a ring buffer. Packets are stored head-to-toe in the re-
ceive buffer, as they are in the transmit buffer. However, each
packet in the receive buffer is aligned on an eight-byte bound-
ary. As packets are being stored in the receive buffer, as the end
of the linear addressing space is reached, the chip’s receive
write pointer automatically wraps around to the top of the re-
ceive addressing range to make a seamless ring. The receive
read pointer does the same as the packets are read out to the sys-
tem. By programming the sizes allocated to transmit and re-
ceive buffers, an optimum usage of the memory can be selected
according to the demands of a particular application.
The buffer controller keeps track of buffer memory partition-
ing and allocation and updates internal address pointers auto-
matically for the tasks of transmit, retransmit, receive, rejec-
tion of packets with errors and data transfers to and from the
host. The host and its drivers are thus relieved of buffer man-
agement functions, making the MB86964 easy to operate and
substantially reducing software requirements. Packets with er-
rors are normally automatically rejected by the MB86964 as
are packets shorter than the IEEE minimum length packet of 60
bytes, excluding Preamble and CRC. Since these tasks can be
done faster in hardware than in software, this not only off-loads
the host system, but it also speeds up the communication pro-
cesses, yielding higher throughput.
As a result, the MB86964
can typically win benchmark performance tests over compet-
ing controllers.
Arbitration of Buffer Access
The buffer controller automatically prioritizes and services re-
quests for access to memory from the transmitter, receiver and
host system. The MB86964’s arbitration mechanism, illus-
trated in Figure 6, interleaves accesses to the buffer memory so
that the operation appears to be simultaneous: data can be writ-
ten to or read from the buffer memory by the host via Buffer
Memory Port Register 8 (BMPR8), while data is being read
from the buffer by the transmitter and/or written in for storage
by the receiver. Each interface, whether host system or net-
work access, appears to be served independently by the con-
troller. Each interface has an associated FIFO to provide time
for the buffer interleaving. Thus, packet data is pipelined
through the system for highest performance and throughput,
and the buffer controller supports all the cases of simultaneous
access to the buffer memory as follows:
1. Data from the network is stored in the receive buffer.
2. The host retreives packets from the receive buffer.
3. The host loads packet data into the transmit buffer.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MB86965 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:EtherCoupler ETHERNET CONTROLLER WITH 10BASE?T TRANSCEIVER |
| MB86965B | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:EtherCoupler ETHERNET CONTROLLER WITH 10BASE?T TRANSCEIVER |
| MB86965BPF-G-BND | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:EtherCoupler ETHERNET CONTROLLER WITH 10BASE?T TRANSCEIVER |
| MB86967 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:LAN Controller with PC Card, ISA Bus, and General-purpose Bus Interfaces |
| MB86967PFV | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:LAN Controller with PC Card, ISA Bus, and General-purpose Bus Interfaces |
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