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| 型號： | MB86964PFV-G |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100 |
| 封裝： | SHRINK, PLASTIC, QFP-100 |
| 文件頁數(shù)： | 39/52頁 |
| 文件大小： | 373K |
| 代理商： | MB86964PFV-G |
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MB86964
44
Table 35. Write Cycle
t1
t3
t2
t5
t4
t6
t8
t7
t9
SA<3:0>
CS
RD
RDY
SD<15:0>
SYMBOL
PARAMETER DESCRIPTION
MINIMUM
MAXIMUM
UNITS
t1
SA<3:0> valid to WR low; CS low to WR low.
3
ns
t2
WR high to SA<3:0> invalid; WR high to CS high.
3
ns
t3
WR low pulse width.
36
ns
t4
WR low to RDY low.
0
26
ns
t5
WR low to RDY high:
ns
For registers and buffer port when port is ready before the write
cycle begins.
0
7
ns
For port access only, if system attempts to make contiguous sys-
tem write cycles at less than 100-ns intervals, and both the trans-
mitter and receiver are active in loopback reception.
0
175
ns
t6
WR low to RDY low.
ns
For all registers.
0
28
ns
For port access only, if system attempts to make contiguous sys-
tem write cycles at less than 100-ns intervals, and transmitter
and receiver are active in loopback reception.
0
175
ns
t7
WR high to RDY high.
28
ns
t8
SD<15:0> valid to WR high.
5
ns
t9
WR high to SD<15:0> invalid.
6
ns
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