參數(shù)資料
型號(hào)： MB86964PFV-G
元件分類(lèi)： 微控制器/微處理器
英文描述： 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100
封裝： SHRINK, PLASTIC, QFP-100
文件頁(yè)數(shù)： 27/52頁(yè)
文件大?。?/td> 373K
代理商： MB86964PFV-G
MB86964
33
CONFIGURATION REGISTERS 0 AND 1
As shown in Tables 18 and 19, system configuration bits are
found in these two registers. Among the configuration controls
found here are physical memory size, partitioning between
transmit and receive buffers, widths of system bus, byte lane
control, and power down control. Most configuration parame-
ters are programmed only during initialization, after power
start and hardware reset.
Software engineers who want to use the same driver code for
the MB86960/64/65 controllers from Fujitsu should note that
the driver can determine which chip is being used by reading
DLCR7 and DLCR6 after hardware reset. The MB86964 reads
60B6H or 70B6H (60H or 70H for DLCR7 and B6H for
DLCR6); the MB86965 reads E0B6H or F0B6H; the
MB86960 reads 30B6H or 20B6H.
Power down mode saves power when the MB86964 is not in
use. When ready to place the MB86964 chip in power down
mode, first write 1 to DLC EN, DLCR6<7>, to turn off the re-
ceiver and transmitter, then write 0 to PWRDN, DLCR7<5>.
To exit the power down mode, write 1 to PWRDN. Register
contents are preserved, unless the chip is hardware reset. Hard-
ware reset also terminates the power down mode.
Byte ordering determines in which portion of the data bus the
high and low bytes of a word are contained. Refer to the System
Interface section for additional information.
Table 18. DLCR6 - Configuration Register 0
BIT
SYMBOL
TYPE
DESCRIPTION
7
DLC EN
RW1
DATA LINK CONTROL ENABLE : When low, enables MB86964 receiver and transmitter
sections. This bit must be set high during initialization, and set low to enable loopback test-
ing and operation on the network. Program Node ID and Hash Table only when this bit is
high.
6
1
RW0
Must be set to ‘1’.
5
SB/ SW
RW1
SYSTEM BYTE/WORD BUS WIDTH: When high, system bus will operate in 8-bit data
mode; when low, 16-bit data mode is selected. The inverse of this bit is output on the SW
pin.
4
1
RW1
Must be set to ‘1’.
3
2
TBS1
TBS0
RW0
RW1
TRANSMIT BUFFER SIZE: Selects size of transmit buffers.
TBS1:TBS0
TRANSMIT
BUFFER
QUANTITY
SIZE, EACH TX
BUFFER
(KBYTES)
SIZE, TOTAL TX
BUFFER (KBYTES)
00
1
2
2
01
2
2
4
10
2
4
8
11
2
8
16
1
0
BS1
BS0
RW1
RW0
BUFFER SIZE: Selects physical size of the SRAM used for the packet buffer.
BS1
BS0
SRAM SIZE (KBYTES)
0
0
8
0
1
Not valid
1
0
32
1
1
Not valid
相關(guān)PDF資料
PDF描述
MB86965 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP16
MB86976PF-G 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP144
MB87033BPF SCSI BUS CONTROLLER, PQFP80
MB8867P 21.33 MHz, PROC SPECIFIC CLOCK GENERATOR, PDIP24
MB88R157A OTHER CLOCK GENERATOR, PDSO8
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MB86965 制造商:FUJITSU 制造商全稱(chēng):Fujitsu Component Limited. 功能描述:EtherCoupler ETHERNET CONTROLLER WITH 10BASE?T TRANSCEIVER
MB86965B 制造商:FUJITSU 制造商全稱(chēng):Fujitsu Component Limited. 功能描述:EtherCoupler ETHERNET CONTROLLER WITH 10BASE?T TRANSCEIVER
MB86965BPF-G-BND 制造商:FUJITSU 制造商全稱(chēng):Fujitsu Component Limited. 功能描述:EtherCoupler ETHERNET CONTROLLER WITH 10BASE?T TRANSCEIVER
MB86967 制造商:FUJITSU 制造商全稱(chēng):Fujitsu Component Limited. 功能描述:LAN Controller with PC Card, ISA Bus, and General-purpose Bus Interfaces
MB86967PFV 制造商:FUJITSU 制造商全稱(chēng):Fujitsu Component Limited. 功能描述:LAN Controller with PC Card, ISA Bus, and General-purpose Bus Interfaces
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*