參數(shù)資料
型號： MB86964PFV-G
元件分類： 微控制器/微處理器
英文描述： 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100
封裝： SHRINK, PLASTIC, QFP-100
文件頁數(shù)： 12/52頁
文件大?。?/td> 373K
代理商： MB86964PFV-G
MB86964
2
LOGIC CONVENTION
Unless otherwise noted, a positive logic (active high) conven-
tion is assumed throughout this document, whereby the pres-
ence at a pin of a higher, more-positive voltage (nominally 5
VDC) causes assertion of the signal. An overbar, e.g., RDY, in-
dicates that the signal is asserted in the low state (nominally 0
volts). Dual-function pins have their alternate function en-
closed in parentheses, e.g., RDY(RDY). Whenever a signal is
separated into numbered bits, e.g., BD7, BD6, BD5, BD4,
BD3, BD2, BD1 and BD0, the family of bits may also be shown
collectively, e.g., as BD<7:0>.
PIN ASSIGNMENTS
VCC
1
BCS
2
BWE
3
BOE
4
BA14
5
BA13
6
BA12
7
BA11
8
BA10
9
BA9
10
BA8
11
BA7
12
GND
13
BA6
14
BA5
15
GND
16
BA4
17
BA3
18
BA2
19
BA1
20
BA0
21
SD15
22
SD7
23
GND
24
SD14
25
75
TPIN
74
TPIP
73
GND
72
TPONB
71
TPONA
70
VCC
69
VCC
68
GND
67
GND
66
TPOPA
65
TPOPB
64
RBIAS
63
GND
62
CLKI
61
CLKO
60
EOP(EOP)
59
INT
58
BHE
57
GND
56
DREQ
55
DMACK
54
RDY(RDY)
53
CS
52
VCC
51
VCC
Vcc
SD6
SD13
SD5
SD12
GND
SD4
SD1
1
SD3
SD10
RDYPOL
26
27
28
29
30
31
32
33
34
35
36
SD2
GND
SD9
SD1
37
38
39
40
41
42
43
44
45
46
47
48
49
50
SD8
SD0
SW
WR
RD
GND
SA3
SA2
SA1
SA0
100
99
98
97
96
95
94
93
92
91
90
GND
BD0
BD1
BD2
BD3
BD4
Vcc
BD5
BD6
BD7
RESET
89
88
87
86
LEDC
LEDL
LEDT
GND
CIN
CIP
Vcc
DON2
DON1
DOP2
DOP1
DIN
DIP
85
84
83
82
81
80
79
78
77
76
MB86964
SQFP100
FTP-100P-M05
TOP VIEW
Figure 1. MB86964 Pin Assignments
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