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| 型號： | MB86964PFV-G |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100 |
| 封裝： | SHRINK, PLASTIC, QFP-100 |
| 文件頁數(shù)： | 40/52頁 |
| 文件大?。?/td> | 373K |
| 代理商： | MB86964PFV-G |
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MB86964
45
Table 36. Single-cycle DMA Timing
t1
t3
t2
t5
t4
t6
t7
DREQ
DMACK
RD or WR
RDY
EOP
SYMBOL
PARAMETER DESCRIPTION
MINIMUM
MAXIMUM
UNITS
t1
DMACK low to DREQ low
0
21
ns
t2
DMACK high to DREQ high
0
19
ns
t3
DMACK low to RD or WR low
0
ns
t4
RD or WR high to DMACK high
3
ns
t5
RD or WR low to EOP low2
0
ns
t6
EOP high to DMACK high2
3
ns
t7
EOP low pulse width2
10
ns
1.
All of the RD, WR and EOP asserted pulses must fall inside of the DMACK asserted pulse. An asserted EOP terminates any further DREQ
after DMACK returns high. The DMA cycle uses DMACK as the chip select.
DMACK overrides SA<3:0>, forcing selection of the buffer
memory port in a DMA cycle.
2.
Timing shown for EOP also applies to EOP when EOP(EOP) is programmed to be asserted high.
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