參數(shù)資料
型號(hào)： MB86964PFV-G
元件分類(lèi)： 微控制器/微處理器
英文描述： 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100
封裝： SHRINK, PLASTIC, QFP-100
文件頁(yè)數(shù)： 49/52頁(yè)
文件大小： 373K
代理商： MB86964PFV-G
MB86964
6
SYSTEM
BUS
DATA
TRANSCEIVER
ADDRESS
DECODER
20 MHz
CRYSTAL
AUI
CONNECTOR
COAXIAL
TRANCEIVER
INTERFACE
TWISTED-PAIR
CONNECTOR
PACKET
BUFFER
SRAM
LEDS
MB86964
TRANSMIT
PAIR
RECEIVE/
COLLISION
PAIRS
10BASE–T
PAIRS
BUFFER
DATA
BUFFER
ADDRESS
SRAM
CONTROL
SYSTEM
DATA
SYSTEM
ADDRESS
SYSTEM CONTROLS
CHIP
SELECT
Figure 3. Typical Application, Block Diagram
MB86964
CLKO
CLKI
20 MHz
20 pF
Figure 4. Crystal Oscillator Connection
CRYSTAL OSCILLATOR
The clock rate of 10 Mbits/s specified by the international LAN
standard, ISO/ANSI/IEEE 8802-3, is derived from an on-chip
oscillator that is controlled by a 20 MHz crystal connected
across pins 61 and 62 (CLKO and CLKI). Capacitance speci-
fied by the crystal manufacturer must be connected as shown in
Figure 4 to stabilize the effects of stray capacitance that may
vary crystal frequency. The 20 MHz clock also serves as an in-
ternal phase-locked loop (PLL) reference for decoder clock re-
covery. Internal clocks shut down when the PWRDN bit,
DLCR7<5>, is asserted for power down mode.
Use a crystal with the following specifications: quartz (AT-
cut); 20-MHz; frequency acurracy of
±50ppm at 25° C and
±100ppm at 0°C to 70°C; parallel resonant with 20 pF-load in
fundamental mode. Possible vendors include: Ecliptek Corp.
(Costa Mesa, CA), p/n ECSM 20.000M; and M-tron Industries,
Inc. (Yankton, SD), p/n MP-1 and MP-2.
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