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參數(shù)資料
| 型號(hào)： | MB86964PFV-G |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100 |
| 封裝： | SHRINK, PLASTIC, QFP-100 |
| 文件頁數(shù)： | 23/52頁 |
| 文件大?。?/td> | 373K |
| 代理商： | MB86964PFV-G |
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MB86964
3
PIN DESCRIPTIONS
System Bus Interface Pins
PIN NO.
SYMBOL
TYPE
DESCRIPTION
22, 25, 28, 30, 33, 35,
39, 41, 23, 27, 29, 32,
34, 37, 40, 42
SD<15:0>
I/O
SYSTEM DATA: All data, command, and status transfers take place over this
bus.
47-50
SA<3:0>
I
SYSTEM ADDRESS: Selects an internal register or port for read/write opera-
tions.
58
BHE
I
BUS HIGH ENABLE: Active low. This pin is the byte/word control line. It is
used only when the MB86964 is configured for a 16-bit data bus by the SB/SW
bit, DLCR6<5>. It allows word, upper byte only or lower byte only transfers.
Address pin SA0 is used with BHE for byte or word transfers as follows:
SB/SW
BHE
SA0
FUNCTION
0
0
0
Word transfer
0
0
1
Byte transfer on upper half of
data bus (SD15-8)
0
1
0
Byte transfer on lower half of
data bus (SD7-0)
0
1
1
Reserved
1
X
X
Byte transfer (SD7-0)
53
CS
I
CHIP SELECT: Active low signal used to select the MB86964.
90
RESET
I
CHIP RESET: Resets the chip’s buffer memory pointers and initializes internal
registers and logic.
45
RD
I
READ STROBE: Active low signal from the system bus which indicates that
the current bus cycle is a read operation.
44
WR
I
WRITE STROBE: Active low signal from the system bus which indicates that
the current bus cycle is a write operation.
56
DREQ
O
DMA REQUEST: Issued to the external DMA controller to indicate that the
MB86964 is ready to transfer data. Used for both read and write operations.
60
EOP(EOP)
I
END OF PROCESS: When asserted by the DMA controller, indicates that the
current DMA process has completed. Asserted state is programmed via
DLCR7<1>. See also DCLR4<2>.
55
DMACK
I
DMA ACKNOWLEDGE: Active low signal which indicates that the DMA con-
troller is ready to transfer data between the host system and the MB86964’s
buffer memory.
59
INT
O
INTERRUPT REQUEST: Active low signal indicates that the MB86964 re-
quires host attention after successful transmission or reception of a packet,
after the completion of a DMA cycle, or if any error conditions occur.
54
RDY(RDY)
O
READY: This signal indicates to the host that MB86964 is ready to complete
the requested read or write operation. The asserted state of this pin is pro-
grammed by RDYPOL, pin 36.
43
SW
O
SYSTEM WORD BUS WIDTH: When low, the system bus interface is pro-
grammed to operate in 8-bit mode; when high,16-bit mode is selected. Inverse
of the value programmed in DLCR6<5>.
36
RDYPOL
I
READY LINE POLARITY SELECT: Controls asserted state of the RDY(RDY)
signal at pin 54, where low selects active low READY (RDY) and high selects
active high READY (RDY).
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