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參數(shù)資料
| 型號(hào)： | MB86964PFV-G |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100 |
| 封裝： | SHRINK, PLASTIC, QFP-100 |
| 文件頁數(shù)： | 45/52頁 |
| 文件大小： | 373K |
| 代理商： | MB86964PFV-G |
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MB86964
5
FUNCTIONAL DESCRIPTION
The MB86964 comprises five major functional blocks: system
interface, buffer controller, transmitter, receiver and control
and status registers, as illustrated in Figure 2. The MB86964’s
receive and transmit sections fully implement the ISO/ANSI/
IEEE 8802-3 CSMA/CD specification for 10 megabit per se-
cond Ethernet. The transmitter assembles data packets for
transmission and the receiver disassembles received data pack-
ets. On-chip Ethernet protocol functions include: automatic
generation and stripping of the 64-bit preamble, generation and
verification of 32-bit cyclic redundancy check (CRC), colli-
sion resolution by binary exponential backoff and retransmis-
sion, several modes of address recognition, error detection and
reporting, and serial/parallel and parallel/serial conversions.
TYPICAL APPLICATION
Figure 3 is a block diagram illustrating use of the MB86964 in
an embedded Ethernet adapter application. One or two 8-bit bi-
directional transceivers (if required) provide data buffering be-
tween the MB86964 and the 8- or 16-bit system bus.
A single 8
or 32 kbyte SRAM implements the local packet buffer. The
MB86964 provides interfaces to 100- or 150-ohm twisted pair
(10BASE-T) as well as direct AUI capability (10BASE5). An
optional coaxial transceiver interface provides additional ca-
pability for Thin Ethernet (10BASE2) networks.
The
MB86964 directly drives three LEDs which provide indication
of operational status.
As shown in the typical application, the MB86964 allows a
highly integrated system configuration. The MB86964’s ar-
chitecture and high level of integration facilitate packet man-
agement and storage, and eliminate the need for a local micro-
processor. The MB86964 connects with the host system bus to
provide command and status interfaces as well as packet data
access. The host processor can directly access command and
status registers mapped into the host I/O or memory space.
Data packets to be transmitted to the network initially transfer
from host memory through a register in the MB86964 into the
dedicated buffer memory where they are temporarily stored
until transmitted. Buffer memory initially stores received data
packets that are later transferred to the host memory.
For detailed design information on a typical adapter board ap-
plication, refer to the Hardware Reference Manual included in
the DK86964 Designer’s Kit which is available for purchase
from your authorized Fujitsu Microelectronics sales represen-
tative or distributor. Please check the “How to Buy” section @
www.fujitsumicro.com/buy/buy.html or contact the Customer
Response Center @ 1–800–866–8608 for more details.
HOST
SYSTEM
INTERFACE
CONTROL
MANCHESTER
ENCODER/
DECODER,
TWISTED–
PAIR
TRANSCEIVER
AND AUI
SD<15:0>
BHE
DATA
LINK
CONTROLLER
DATA
LINK
CONTROL
REGISTERS
BUFFER
MANAGER
AND SRAM
INTERFACE
BUFFER
MANAGER
AND HASH
TABLE
REGISTERS
SA<3:0>
RD
WR
CS
DMACK
EOP(EOP)
INT
DREQ
RESET
RDYPOL
SW
RDY(RDY)
BD<7:0>
BCS
BA<14:0>
BWE
BOE
LEDs (3)
TPOP
TPON
TPIP
TPIN
RBIAS
CLKI
CLKO
DIP
DIN
CIP
CIN
DOP
DON
TWISTED
PAIR
AUI
CONTROL
TX DATA
RX DATA
Figure 2. MB86964 Block Diagram
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| MB86965 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:EtherCoupler ETHERNET CONTROLLER WITH 10BASE?T TRANSCEIVER |
| MB86965B | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:EtherCoupler ETHERNET CONTROLLER WITH 10BASE?T TRANSCEIVER |
| MB86965BPF-G-BND | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:EtherCoupler ETHERNET CONTROLLER WITH 10BASE?T TRANSCEIVER |
| MB86967 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:LAN Controller with PC Card, ISA Bus, and General-purpose Bus Interfaces |
| MB86967PFV | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:LAN Controller with PC Card, ISA Bus, and General-purpose Bus Interfaces |
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