953
SAM4CP [DATASHEET]
43051E–ATPL–08/14
41.4.6 Security Features
41.4.6.1 Unspecified Register Access Detection
When an unspecified register access occurs, the URAD flag in the AES_ISR is raised. Its source is then reported in the
Unspecified Register Access Type (URAT) field. Only the last unspecified register access is available through the URAT
field.
Several kinds of unspecified register accesses can occur:
Input Data Register written during the data processing when SMOD = IDATAR0_START.
Output Data Register read during data processing.
Mode Register written during data processing.
Output Data Register read during sub-keys generation.
Mode Register written during sub-keys generation.
Write-only register read access.
The URAD bit and the URAT field can only be reset by the SWRST bit in the AES_CR.
41.5
Advanced Encryption Standard (AES) User Interface
Table 41-5.
Register Mapping
Offset
Register
Name
Access
Reset
0x00
Control Register
AES_CR
Write-only
–
0x04
Mode Register
AES_MR
Read/Write
0x0
0x08 - 0x0C
Reserved
–
–
–
0x10
Interrupt Enable Register
AES_IER
Write-only
–
0x14
Interrupt Disable Register
AES_IDR
Write-only
–
0x18
Interrupt Mask Register
AES_IMR
Read-only
0x0
0x1C
Interrupt Status Register
AES_ISR
Read-only
0x0000001E
0x20
Key Word Register 0
AES_KEYWR0
Write-only
–
0x24
Key Word Register 1
AES_KEYWR1
Write-only
–
0x28
Key Word Register 2
AES_KEYWR2
Write-only
–
0x2C
Key Word Register 3
AES_KEYWR3
Write-only
–
0x30
Key Word Register 4
AES_KEYWR4
Write-only
–
0x34
Key Word Register 5
AES_KEYWR5
Write-only
–
0x38
Key Word Register 6
AES_KEYWR6
Write-only
–
0x3C
Key Word Register 7
AES_KEYWR7
Write-only
–
0x40
Input Data Register 0
AES_IDATAR0
Write-only
–
0x44
Input Data Register 1
AES_IDATAR1
Write-only
–
0x48
Input Data Register 2
AES_IDATAR2
Write-only
–
0x4C
Input Data Register 3
AES_IDATAR3
Write-only
–
0x50
Output Data Register 0
AES_ODATAR0
Read-only
0x0
0x54
Output Data Register 1
AES_ODATAR1
Read-only
0x0
0x58
Output Data Register 2
AES_ODATAR2
Read-only
0x0