137
SAM4CP [DATASHEET]
43051E–ATPL–08/14
cond
is an optional condition code, see
“Conditional Execution”
.
RdHi, RdLo
are the destination registers. For UMLAL and SMLAL they also hold the accumulating value.
Rn, Rm
are registers holding the operands.
Operation
The UMULL instruction interprets the values from
Rn
and
Rm
as unsigned integers. It multiplies these integers and
places the least significant 32 bits of the result in
RdLo
, and the most significant 32 bits of the result in
RdHi
.
The UMLAL instruction interprets the values from
Rn
and
Rm
as unsigned integers. It multiplies these integers, adds the
64-bit result to the 64-bit unsigned integer contained in
RdHi
and
RdLo
, and writes the result back to
RdHi
and
RdLo
.
The SMULL instruction interprets the values from
Rn
and
Rm
as two’s complement signed integers. It multiplies these
integers and places the least significant 32 bits of the result in
RdLo
, and the most significant 32 bits of the result in
RdHi
.
The SMLAL instruction interprets the values from
Rn
and
Rm
as two’s complement signed integers. It multiplies these
integers, adds the 64-bit result to the 64-bit signed integer contained in
RdHi
and
RdLo
, and writes the result back to
RdHi
and
RdLo
.
Restrictions
In these instructions:
Do not use SP and do not use PC.
RdHi
and
RdLo
must be different registers.
Condition Flags
These instructions do not affect the condition code flags.
Examples
UMULL R0, R4, R5, R6 ; Unsigned (R4,R0) = R5 x R6
SMLAL R4, R5, R3, R8 ; Signed (R5,R4) = (R5,R4) + R3 x R8
12.6.6.12 SDIV and UDIV
Signed Divide and Unsigned Divide.
Syntax
SDIV{
cond
} {
Rd
,}
Rn
,
Rm
UDIV{
cond
} {
Rd
,}
Rn, Rm
where:
cond
is an optional condition code, see
“Conditional Execution”
.
Rd
is the destination register. If
Rd
is omitted, the destination register is
Rn
.
Rn
is the register holding the value to be divided.
Rm
is a register holding the divisor.
Operation
SDIV performs a signed integer division of the value in
Rn
by the value in
Rm
.
UDIV performs an unsigned integer division of the value in
Rn
by the value in
Rm
.
For both instructions, if the value in
Rn
is not divisible by the value in
Rm
, the result is rounded towards zero.
Restrictions
Do not use SP and do not use PC
.
Condition Flags
These instructions do not change the flags.
Examples
SDIV R0, R2, R4 ; Signed divide, R0 = R2/R4
UDIV R8, R8, R1 ; Unsigned divide, R8 = R8/R1