695
SAM4CP [DATASHEET]
43051E–ATPL–08/14
TWI continues receiving data until a STOP condition or a REPEATED START + an address different from SADR is
detected. Note that at the end of the write sequence TXCOMP flag is set and SVACC reset.
See
Figure 34-27 on page 696
.
Clock Synchronization Sequence
In TWI_RHR is not read in time, theTWI performs a clock synchronization.
Clock synchronization information is given by the bit SCLWS (Clock Wait state).
See
Figure 34-30 on page 698
.
Clock Stretching Sequence
In TWI_THR is not written in time, the TWI performs a clock stretching.
Clock stretching information is given by the bit SCLWS (Clock Wait state).
See
Figure 34-29 on page 697
.
General Call
In the case where a GENERAL CALL is performed, the GACC (General Call Access) flag is set.
After GACC is set, the user must interpret the meaning of the GENERAL CALL and decode the new address
programming sequence.
See
Figure 34-28 on page 696
.
34.7.5.5 Data Transfer
Read Operation
The read mode is defined as a data requirement from the master.
After a START or a REPEATED START condition is detected, the decoding of the address starts. If the slave address
(SADR) is decoded, SVACC is set and SVREAD indicates the direction of the transfer.
Until a STOP or REPEATED START condition is detected, TWI continues sending data loaded in the TWI_THR.
If a STOP condition or a REPEATED START + an address different from SADR is detected, SVACC is reset.
Figure 34-26
describes the write operation.
Figure 34-26. Read Access Ordered by a MASTER
Notes: 1.
When SVACC is low, the state of SVREAD becomes irrelevant.
TXRDY is reset when data has been transmitted from TWI_THR to the internal shifter and set when this
data has been acknowledged or non acknowledged.
2.
Write THR
Read RHR
SVREAD has to be taken into account only while SVACC is active
TWD
TXRDY
NACK
SVACC
SVREAD
EOSVACC
SADR
S
ADR
R
NA
R
A
DATA
A
A
DATA
NA
S/Sr
DATA
NA
P/S/Sr
SADR matches,
TWI answers with an ACK
SADR does not match,
TWI answers with a NACK
ACK/NACK from the Master