SAM4CP [DATASHEET]
43051E–ATPL–08/14
10
Notes: 1.
VDDLCD must be inferior or equals to (VDDIO/VDDIN - 100mv) if VDDLCD is powered externally.
See “Typical Powering Schematics” Section for restrictions on voltage range of Analog Cells.
See
Table 45-5 on page 1009
.
See
Table 45-11 on page 1018
.
Different configurations allowed depending on external topology and net behavior.
Depending on whether an isolated or a non-isolated power supply is being used, isolation of this pin should
be taken into account in the circuitry design. Please refer to the Reference Design for further information.
2.
3.
4.
5.
6.
Pulse Width Modulation Controller - PWMC
PWMx
PWM Waveform Output for channel x
Output
VDDIO
Serial Peripheral Interface - SPI
SPI1_MISO
Master In Slave Out
I/O
VDDIO
SPI1_MOSI
Master Out Slave In
I/O
SPI1_SPCK
SPI Serial Clock
I/O
SPI1_NPCS0
SPI Peripheral Chip Select 0
I/O
Low
NPCS0 is also NSS for
slave mode
SPI1_NPCS1 -
SPI1_NPCS3
SPI Peripheral Chip Select
Output
Low
Segmented LCD Controller - SLCDC
COM[4:0]
Common Terminals
Output
VDDIO
SEG49
SEG[47:3]
Segment Terminals
Output
Two-Wire Interface - TWI
TWDx
TWIx Two-wire Serial Data
I/O
VDDIO
TWCKx
TWIx Two-wire Serial Clock
I/O
Analog
ADVREF
External Voltage Reference for ADC
Analog
10-bit Analog-to-Digital Converter - ADC
AD0 - AD1
AD3 - AD5
Analog Inputs
Analog
Digital
VDDIO
ADC input range limited
to [0 - ADVREF]
ADTRG
ADC Trigger
Input
Fast Flash Programming Interface - FFPI
PGMEN0-PGMEN1
Programming Enabling
Input
VDDIO
PGMM0-PGMM3
Programming Mode
PGMD0-PGMD15
Programming Data
I/O
PGMRDY
Programming Ready
Output
High
PGMNVALID
Data Direction
Low
PGMNOE
Programming Read
Input
Low
PGMNCMD
Programming Command
Low
Table 3-1.
Signal Description List (Continued)
Signal Name
Function
Type
Active
Level
Voltage
reference
Comments