170
SAM4CP [DATASHEET]
43051E–ATPL–08/14
Operation
This instruction:
1.
2.
Negates a floating-point value.
Places the results in a second floating-point register.
The floating-point instruction inverts the sign bit.
Restrictions
There are no restrictions.
Condition Flags
These instructions do not change the flags.
12.6.11.23 VNMLA, VNMLS, VNMUL
Floating-point multiply with negation followed by add or subtract.
Syntax
VNMLA{
cond
}.F32
Sd
,
Sn
,
Sm
VNMLS{
cond
}.F32
Sd
,
Sn
,
Sm
VNMUL{
cond
}.F32 {
Sd
,}
Sn
,
Sm
where:
cond
is an optional condition code, see
“Conditional Execution”
.
Sd
is the destination floating-point register.
Sn, Sm
are the operand floating-point registers.
Operation
The VNMLA instruction:
1.
2.
3.
Multiplies two floating-point register values.
Adds the negation of the floating-point value in the destination register to the negation of the product.
Writes the result back to the destination register.
The VNMLS instruction:
1.
2.
3.
Multiplies two floating-point register values.
Adds the negation of the floating-point value in the destination register to the product.
Writes the result back to the destination register.
The VNMUL instruction:
1.
2.
Multiplies together two floating-point register values.
Writes the negation of the result to the destination register.
Restrictions
There are no restrictions.
Condition Flags
These instructions do not change the flags.
12.6.11.24 VPOP
Floating-point extension register Pop.
Syntax
VPOP{
cond
}{.
size
}
list
where:
cond
is an optional condition code, see
“Conditional Execution”
.
size
is an optional data size specifier.
If present, it must be equal to the size in bits, 32 or 64, of the registers in
list
.