465
SAM4CP [DATASHEET]
43051E–ATPL–08/14
27.8.3 PHY Layer Registers
27.8.3.1 PHY Configuration Registers
27.8.3.1.1 PHY Layer Special Function Register
Name:
PHY_SFR
Address:
0xFE2A
Access:
Read/write
Reset:
0x87
BCH_ERR: Busy Channel Error Flag
This bit is cleared to ‘0’ by hardware to indicate the presence of an OFDM signal at the transmission instant.
Otherwise, this field value is ‘1’.
This bit is used for returning a result of “Busy Channel” in the PHY_DATA confirm primitive (see PRIME specifi-
cation).
CD: Carrier Detect bit
This bit is set to ‘1’ by hardware when an OFDM signal is detected, and it is active during the whole reception.
This bit is used in channel access (CSMA-CA algorithm) for performing channel-sensing.
UMD: Unsupported Modulation Scheme flag
This flag is set to ‘1’ by hardware every time a header with correct CRC is received, but the PROTOCOL field in
this header indicates a modulation scheme not supported by the system.
INT_PHY: Physical Layer interruption
This bit is internally connected to the EINT pin.
It is Low level active and it is set to '0' by the PHY layer to trigger an interrupt in the external host.
In reception, every time a PLC message is received, the PHY layer generates two interrupts. One of them
when the physical header is correctly received (two first symbols), and the other one when the message is
completely received.
In transmission, an interrupt will be generated every time a complete message has been sent.
The signal is cleared by writing '1' in the bit PHY_SFR(0).
7
6
5
4
-
3
-
2
-
1
-
0
BCH_ERR
CD
UMD
INT_PHY