533
SAM4CP [DATASHEET]
43051E–ATPL–08/14
29.5.7 Main Clock Frequency Counter
The device features a Main Clock frequency counter that provides the frequency of the Main Clock.
The Main Clock frequency counter is reset and starts incrementing at the Main Clock speed after the next rising edge of
the Slow Clock in the following cases:
When the 4/8/12 MHz Fast RC Oscillator clock is selected as the source of Main Clock and when this oscillator
becomes stable (i.e., when the MOSCRCS bit is set).
When the 3 to 20 MHz Crystal or Ceramic Resonator-based Oscillator is selected as the source of Main Clock and
when this oscillator becomes stable (i.e., when the MOSCXTS bit is set).
When the Main Clock Oscillator selection is modified.
When the RCMEAS bit of CKGR_MFCR is written to 1.
Then, at the 16th falling edge of Slow Clock, the MAINFRDY bit in the Clock Generator Main Clock Frequency Register
(CKGR_MCFR) is set and the counter stops counting. Its value can be read in the MAINF field of CKGR_MCFR and
gives the number of Main Clock cycles during 16 periods of Slow Clock, so that the frequency of the 4/8/12 MHz Fast RC
Oscillator or 3 to 20 MHz Crystal or Ceramic Resonator-based Oscillator can be determined.
29.6
Divider and PLL Blocks
The device features one Divider/two PLL Blocks that permit a wide range of frequencies to be selected on either the
master clock, the processor clock or the programmable clock outputs.
Figure 29-4
shows the block diagram of the divider
and PLL blocks.
Figure 29-4.
Divider and PLL Blocks Diagram
Divider B
DIVB
PLL B
MULB
PLL A
Counter
PLLBCOUNT
LOCKB
PLL A
Counter
PLLACOUNT
LOCKA
MULA
SLCK
PLLACK
PLLBCK
PLL B
MAINCK
PLLBDIV2
SRCB
0
1
SLCK
PLLADIV2
CKGR_PLLBR
CKGR_PLLAR
CKGR_PLLAR
CKGR_PLLBR
CKGR_PLLBR
PMC_SR
PMC_SR
PMC_MCKR
PMC_MCKR
CKGR_PLLBR