1043
SAM4CP [DATASHEET]
43051E–ATPL–08/14
VDDIO = VDDIN = 3.3V.
VDDCORE = 1.2V (Internal Voltage regulator used).
T
A
= 25°C.
Core 0 clock (HCLK) and Core 1 (CPHCLK) clock stopped.
Sub-system 0 Master Clock (MCK), Sub-system 1 Master Clock (CPBMCK) running at various frequencies (PLLB
used for frequencies above 12 MHz, fast RC oscillator at 12 MHz for the 12 MHz point, and Fast RC oscillator at 8
MHz divided by 1/2/4/8/16/32 for lower frequencies).
All peripheral clocks deactivated.
No activity on I/O lines.
PLC in shutdown.
VDDPLL not taken into account. See PLL characteristics for further details.
Current measurement as per
Figure 45-17
.
45.7.4 Active Mode Power Consumption
The current consumption configuration for active mode, i.e., Core executing codes, are as follow:
VDDIO = VDDIN = 3.3V.
VDDCORE = 1.2V (Internal Voltage regulator used).
T
A
= 25°C.
Sub-system 0 Master Clock (MCK) and Core Clock (HCLK), Sub-system 1 Master Clock (CPBMCK) and Core
Clock (CPHCLK) running at various frequencies (PLLB used for frequencies above 8 MHz and Fast RC oscillator
at 8 MHz divided by 1/2/4/8/16/32 for lower frequencies).
All Peripheral clocks are deactivated.
No activity on I/O lines.
PLC in shutdown.
Flash Wait State (FWS) in EEFC_FMR adjusted versus Core Frequency.
Current measurement as per
Figure 45-18
.
Table 45-47. Typical Sleep Mode current consumption versus Frequency
Master Clock (MHz)
IDD_IN - AMP1
IDD_IO - AMP2
IDD_CORE - AMP3
Unit
120
14.26
0.03
10.83
mA
100
11.96
0.03
9.09
84
10.1
0.03
7.68
64
7.78
0.03
5.92
48
5.93
0.03
4.48
32
5.02
0.03
3.16
24
3.85
0.03
2.4
12
1.26
0.03
1.21
8
0.88
0.03
0.83
4
0.5
0.03
0.45
2
0.32
0.03
0.27
1
0.26
0.03
0.22
0.5
0.22
0.03
0.2
0.25
0.19
0.03
0.18